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Title: Design of CMOS broadband transimpedance amplifiers for 10Gbit/s optical communications
Authors: Lu, Zheng Hao
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
DRNTU::Engineering::Electrical and electronic engineering::Optics, optoelectronics, photonics
DRNTU::Engineering::Electrical and electronic engineering::Electronic apparatus and materials
Issue Date: 2007
Source: Lu, Z. H. (2007). Design of CMOS broadband transimpedance amplifiers for 10Gbit/s optical communications. Doctoral thesis, Nanyang Technological University, Singapore.
Abstract: The dramatic growth of data transportation volume and speed over Internet in recent years entails the development of low cost integrated optical communication systems with ever-increasing transmission bandwidth. Currently, the most successful commercial high-speed digital communication protocol is SONET (Synchronous Optical Network) OC-192 while the 10Gb/s Ethernet (IEEE802.3ae) is also emerging as an alternative for point-to-point applications. Therefore, optical communication systems operating at 10Gb/s are of great interest. Transimpedance amplifiers are extensively exploited as the front-end of optical communication receivers. Traditionally, such front-end circuits and devices are heavily dependent on III-V technologies due to their speed and noise advantages. However, the demand for high volume, wide deployment of optical components in recent years makes silicon based integrated circuits the most economical solution. CMOS appears to be the best candidate for fully integrated Transimpedance Amplifier (TIA) design due to its cost, integration and manufacturability advantages and providing reasonable speed, noise performances at the same time. This work examines the technical challenges and explores various broadband design techniques in implementing transimpedance amplifiers using cost effective CMOS technology. Based on these proposed and existing broadband design techniques, two prototypes of 10Gb/s transimpedance amplifiers are implemented using Chartered Semiconductor (CHRT) 0.18 µm CMOS process, which achieve comparable performance to those III-V and SiGe counterparts in most aspects while possessing the merits of CMOS technology.
DOI: 10.32657/10356/13323
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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