Please use this identifier to cite or link to this item:
https://hdl.handle.net/10356/13350
Title: | I/O buffer model development from IBIS and IMIC for simulation in SPICE | Authors: | Wang, Ying. | Keywords: | DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits DRNTU::Engineering::Computer science and engineering::Computing methodologies::Simulation and modeling |
Issue Date: | 1999 | Abstract: | In today's high-speed and high IC density digital system, many new problems have appeared. One significant issue is signal integrity (SI) which concerns signal purity. Signal noise and signal delay due to interconnect have been becoming to dominate circuit performance. In order to design reliable digital circuits, SI analysis becomes imperative. | URI: | http://hdl.handle.net/10356/13350 | Schools: | School of Electrical and Electronic Engineering | Fulltext Permission: | restricted | Fulltext Availability: | With Fulltext |
Appears in Collections: | EEE Theses |
Files in This Item:
File | Description | Size | Format | |
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WangYing1999.pdf Restricted Access | Main report | 19.29 MB | Adobe PDF | View/Open |
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