Fabrication & characterization of high aspect ratio fine pitch deep reactive ion etched through-wafer electroplated copper interconnects

Abstract

In recent years, through-wafer interconnects have emerged as a critical component required in the fabrication of the next generation of 3-D consumer electronic devices, which will have faster signal processing speed, ultra high I/Os density, smaller foot-print area, improved electrical and thermo-mechanical performance, system level reliability, and many more functionalities than their present ones. Fabrication of 3-D devices utilizes the concept of vertically stacking, wherein specific components like logic, memory, sensors, actuators, A/D converters, etc., are fabricated on separate wafers and then interconnected onto a single wafer-scaled package by through-wafer interconnects. Since, these devices are vertically interconnected, the effective interconnect path is relatively shorter; thus electrical signal takes lesser time in traveling from the bottom device to the top ones. This faster electrical signal propagation results in lower parasitic losses (RC delay), reduced power consumption, higher I/Os density, and improved system performance.