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|Title:||Quantitative analysis of the mechanical and electrical properties of Cu-Cu bonds for three-dimensional integrated circuits (3D ICs).||Authors:||Leong, Hoi Liong.||Keywords:||DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits||Issue Date:||2007||Source:||Leong, H. L. (2007). Quantitative analysis of the mechanical and electrical properties of Cu-Cu bonds for three-dimensional integrated circuits (3D ICs). Doctoral thesis, Nanyang Technological University, Singapore.||Abstract:||The increasing complexity and the scaling down of feature sizes for devices have led to the increasing dominance of interconnect delays in determining integrated circuit performance. One promising solution is to stack devices vertically, commonly known as 3D ICs. Copper is an attractive candidate for 3D applications as it can be both the bonding and interconnect material. This thesis explores the wafers bonding technique, thermocompression bonding, to create 3D ICs. This technique involves the application of pressure and temperature to forge a bond. In this work, copper thin films were used to bond two silicon substrates. Characterization of the bond process focused on the effects of bonding temperature (250oC to 400oC), applied load (400 to 10000 N) and surface roughness (total root-mean-square roughness of 1 nm to 14 nm). The resultant bond was quantified using a four-point bend test technique. High bond strength was obtained and the bond quality was found to improve with increases in the bond temperature and applied load, and with decreases in the surface roughness. However, nonideality in the load-displacement behavior was observed due to variation in the bond strengths and non-uniformity in the bonding. This is attributed to process issues such as dishing and non-uniform distribution of the true contact area.||URI:||http://hdl.handle.net/10356/13607||Fulltext Permission:||open||Fulltext Availability:||With Fulltext|
|Appears in Collections:||SMA Theses|
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