Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/136843
Title: Analysis of circuit aging on accuracy degradation of deep neural network accelerator
Authors: Liu, Wenye
Chang, Chip-Hong
Keywords: Engineering::Electrical and electronic engineering::Integrated circuits
Issue Date: 2019
Source: Liu, W. & Chang, C.-H. (2019). Analysis of circuit aging on accuracy degradation of deep neural network accelerator. 2019 IEEE International Symposium on Circuits and Systems (ISCAS). doi:10.1109/ISCAS.2019.8702226
Project: MOE2015-T2-2-013
Abstract: Deep neural networks have achieved phenomenal successes in vision recognition tasks, which motivate the deployment of deep learning in portable and smart wearable devices. To overcome the fundamental challenges of power and resource limitation, application-specific integrated circuit accelerators have emerged to compact the model and use lower precision arithmetic to increase the throughput of computation with reduced power consumption. Although very high energy efficiency has been achieved by removing redundant weights, compressing data and even sacrificing timing margin, such trend in hardware acceleration that pushes the deep learning systems to the error threshold can be disastrous for the tasks they performed due to failure or degraded performance of circuit components. Concerned by the lack of attention on the evolving unreliability effects in artificial intelligent accelerators implemented by the continuously scaled CMOS technology, this paper is the first to evaluate the effect of circuit aging on performance degradation of deep learning accelerator. Our findings indicate that DNN system running at their peak throughput rate can experience up to 84% accuracy drop after a year of aging and the accumulation of errors aggravates with the depth of learning. It is also found that relaxation of throughput rate can slow down the loss of classification accuracy considerably.
URI: https://hdl.handle.net/10356/136843
ISBN: 9781728103976
DOI: 10.1109/ISCAS.2019.8702226
Rights: © 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: https://doi.org/10.1109/ISCAS.2019.8702226
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Conference Papers

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