Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/137073
Title: A 10-bit 300 MS/s 5.8 mW SAR ADC with two-stage interpolation for PET imaging
Authors: Qiu, Lei
Wang, Keping
Tang, Kai
Siek, Liter
Zheng, Yuanjin
Keywords: Engineering::Electrical and electronic engineering
Issue Date: 2018
Source: Qiu, L., Wang, K., Tang, K., Siek, L., & Zheng, Y. (2018). A 10-bit 300 MS/s 5.8 mW SAR ADC With two-stage interpolation for PET Imaging. IEEE Sensors Journal, 18(5), 2006-2014. doi:10.1109/JSEN.2018.2790581
Journal: IEEE Sensors Journal
Abstract: In this paper, a high speed low power 2b/cycle successive approximation register (SAR) analog-To-digital converter (ADC) is proposed for medical imaging. The ADC adopts a two-stage differential pair based interpolation technique that can reduce resolution of the capacitive DAC and avoid usage of smaller unit capacitor. A meta-stability immunity technique is proposed to enhance the asynchronous conversion. A design example of 10-bit 2b/cycle SAR ADC with sampling rate up to 300 MS/s is fabricated. Dissipating 5.8 mW with 1.2 V supply and occupying an active area of 0.082 mm2, the measured SFDR and SNDR at Nyquist input are 59-dB and 51.5-dB respectively. It achieves an effective resolution bandwidth of 360 MHz and a figure-of-merit of 61fJ/conversion-step.
URI: https://hdl.handle.net/10356/137073
ISSN: 1530-437X
DOI: 10.1109/JSEN.2018.2790581
Rights: © 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: https://doi.org/10.1109/JSEN.2018.2790581.
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Journal Articles

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