Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/137668
Title: Approximate early output asynchronous adders based on dual-rail data encoding and 4-phase return-to-zero and return-to-one handshaking
Authors: Balasubramanian, Padmanabhan
Keywords: Engineering::Computer science and engineering
Issue Date: 2017
Source: Balasubramanian, P. (2017). Approximate early output asynchronous adders based on dual-rail data encoding and 4-phase return-to-zero and return-to-one handshaking. International Journal of Circuits, Systems and Signal Processing, 11, 445-453.
Journal: International Journal of Circuits, Systems and Signal Processing 
Abstract: Approximate computing is emerging as an alternative to accurate computing due to its potential for realizing digital circuits and systems with low power dissipation, less critical path delay, and less area occupancy for an acceptable trade-off in the accuracy of results. In the domain of computer arithmetic, several approximate adders and multipliers have been designed and their potential have been showcased versus accurate adders and multipliers for practical digital signal processing applications. Nevertheless, in the existing literature, almost all the approximate adders and multipliers reported correspond to the synchronous design method. In this work, we consider robust asynchronous i.e. quasi-delay-insensitive realizations of approximate adders by employing delay-insensitive codes for data representation and processing, and the 4-phase handshake protocols for data communication. The 4-phase handshake protocols used are the return-to-zero and the return-to-one protocols. Specifically, we consider the implementations of 32-bit approximate adders based on the return-to-zero and return-to-one handshake protocols by adopting the delay-insensitive dual-rail code for data encoding. We consider a range of approximations varying from 4-bits to 20-bits for the least significant positions of the accurate 32-bit asynchronous adder. The asynchronous adders correspond to early output (i.e. early reset) type, which are based on the well-known ripple carry adder architecture. The experimental results show that approximate asynchronous adders achieve reductions in the design metrics such as latency, cycle time, average power dissipation, and silicon area compared to the accurate asynchronous adders. Further, the reductions in the design metrics are greater for the return-to-one protocol compared to the return-tozero protocol. The design metrics were estimated using a 32/28nm CMOS technology.
URI: https://hdl.handle.net/10356/137668
ISSN: 1998-4464
Schools: School of Computer Science and Engineering 
School of Electrical and Electronic Engineering 
Rights: © 2017 The Author(s). All rights reserved. This paper was published by NAUN in International Journal of Circuits, Systems and Signal Processing and is made available with permission of The Author(s).
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:SCSE Journal Articles

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