Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/137668
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dc.contributor.authorBalasubramanian, Padmanabhanen_US
dc.date.accessioned2020-04-08T03:10:30Z-
dc.date.available2020-04-08T03:10:30Z-
dc.date.issued2017-
dc.identifier.citationBalasubramanian, P. (2017). Approximate early output asynchronous adders based on dual-rail data encoding and 4-phase return-to-zero and return-to-one handshaking. International Journal of Circuits, Systems and Signal Processing, 11, 445-453.en_US
dc.identifier.issn1998-4464en_US
dc.identifier.urihttps://hdl.handle.net/10356/137668-
dc.description.abstractApproximate computing is emerging as an alternative to accurate computing due to its potential for realizing digital circuits and systems with low power dissipation, less critical path delay, and less area occupancy for an acceptable trade-off in the accuracy of results. In the domain of computer arithmetic, several approximate adders and multipliers have been designed and their potential have been showcased versus accurate adders and multipliers for practical digital signal processing applications. Nevertheless, in the existing literature, almost all the approximate adders and multipliers reported correspond to the synchronous design method. In this work, we consider robust asynchronous i.e. quasi-delay-insensitive realizations of approximate adders by employing delay-insensitive codes for data representation and processing, and the 4-phase handshake protocols for data communication. The 4-phase handshake protocols used are the return-to-zero and the return-to-one protocols. Specifically, we consider the implementations of 32-bit approximate adders based on the return-to-zero and return-to-one handshake protocols by adopting the delay-insensitive dual-rail code for data encoding. We consider a range of approximations varying from 4-bits to 20-bits for the least significant positions of the accurate 32-bit asynchronous adder. The asynchronous adders correspond to early output (i.e. early reset) type, which are based on the well-known ripple carry adder architecture. The experimental results show that approximate asynchronous adders achieve reductions in the design metrics such as latency, cycle time, average power dissipation, and silicon area compared to the accurate asynchronous adders. Further, the reductions in the design metrics are greater for the return-to-one protocol compared to the return-tozero protocol. The design metrics were estimated using a 32/28nm CMOS technology.en_US
dc.language.isoenen_US
dc.relation.ispartofInternational Journal of Circuits, Systems and Signal Processingen_US
dc.rights© 2017 The Author(s). All rights reserved. This paper was published by NAUN in International Journal of Circuits, Systems and Signal Processing and is made available with permission of The Author(s).en_US
dc.subjectEngineering::Computer science and engineeringen_US
dc.titleApproximate early output asynchronous adders based on dual-rail data encoding and 4-phase return-to-zero and return-to-one handshakingen_US
dc.typeJournal Articleen
dc.contributor.schoolSchool of Computer Science and Engineeringen_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.description.versionPublished versionen_US
dc.identifier.arxivarXiv:1801.06070-
dc.identifier.volume11en_US
dc.identifier.spage445en_US
dc.identifier.epage453en_US
dc.subject.keywordsAsynchronous Designen_US
dc.subject.keywordsApproximate Computingen_US
item.grantfulltextopen-
item.fulltextWith Fulltext-
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