Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/138119
Title: Design and analysis of D-Band on-chip modulator and signal source based on split-ring resonator
Authors: Liang, Yuan
Boon, Chirn Chye
Li, Chenyang
Tang, Xiao-Lan
Ng, Herman Jalli
Kissinger, Dietmar
Wang, Yong
Zhang, Qingfeng
Yu, Hao
Keywords: Engineering::Electrical and electronic engineering
Issue Date: 2019
Source: Liang, Y., Boon, C. C., Li, C., Tang, X.-L., Ng, H. J., Kissinger, D., ... Yu, H. (2019). Design and analysis of D-Band on-chip modulator and signal source based on split-ring resonator. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 27(7), 1513-1526. doi:10.1109/TVLSI.2019.2906680
Project: MOE RG86/16
Journal: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Abstract: In an effort towards high-speed and low-power I/O data link in future Exa-scale data server, this paper presents a signal source and a modulator in D-band. Split-ring resonator (SRR) structures are used in both to boost the signal power and extinction ratio (ER). The modulator manifests itself as a compact SRR whose magnetic resonance frequency can be modulated by high speed data. Such a magnetic metamaterial achieves a significant reduction of radiation loss with high ER by stacking two auxiliary SRR unit-cells with interleaved placement. The high-Q tank for oscillation is realized by a stacked SRR decorated with slow-wave transmission line (T-line) for electric field confinement. A 4-ways power combined fundamental 80-GHz coupled-oscillator-network is magnetically synchronized by the slow-wave T-line, which is frequency doubled to 160 GHz. Fabricated in 65-nm CMOS process, the measured results show that: 1) the modulator achieves 3 dB insertion loss at on-state with 43 dB isolation at off-state, leading to a 40-dB ER at 125 GHz within an area of only 40 μm × 67 μm. 2) The signal source achieves 6.3% frequency tuning range (FTR) with 3.7 mW peak output power at 160 GHz within 0.053 mm2 active area. It has a measured phase noise of –105 dBc/Hz at 10 MHz offset, 5.5% DC-to-RF power efficiency, 70.1 mW/mm2 power density, FOM of –171 dBc/Hz and FOMT of –172.7 dBc/Hz.
URI: https://hdl.handle.net/10356/138119
ISSN: 1557-9999
DOI: 10.1109/TVLSI.2019.2906680
Rights: © 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: https://doi.org/10.1109/TVLSI.2019.2906680
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Journal Articles

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