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|Title:||Design automation for camouflage circuits||Authors:||Ng, Chuan Seng||Keywords:||Engineering::Electrical and electronic engineering::Electronic circuits||Issue Date:||2020||Publisher:||Nanyang Technological University||Project:||EE4080||Abstract:||Digital logic circuits are an essential part of any integrated system. However, they are susceptible to malicious parties’ attacks, such as hardware trojans, intellectual property (IP) piracy, reverse engineering. There are various methods available to defend against these attacks, such as integrated circuit (IC) camouflaging, design obfuscation, split manufacturing, but the method adopted in the project is to camouflage the logic gates in the digital logic circuit. Even so, the functionality and security of the camouflaged logic gates must be verified and analysed before affirming that the camouflage choices are optimal at least 50% of the time it is utilized. There are three main contributions in this project. The first is the library cell design for camouflaging. This is especially crucial as it details how and what the chosen library cell will be camouflaged into. Next is the methodology flow, which includes the method to implement and utilize the camouflage library cells. The purpose behind and effect of each chosen library cell will also be explained and illustrated. Lastly is the camouflage IC deterrence analysis. The effectiveness of the deterrence is based on the number of library cells chosen to be camouflaged and their location. An analogy of the library cell placement is roadblocks. It is redundant to set up roadblocks for two paths leading to the same immediate destination. Hence, it is more efficient and effective to ensure that roadblocks are set up at every path leading to the end destination. This would result in the minimal number of roadblocks needed to cover the maximum number of paths. This implementation would also lead to a reduced impact on the key parameters of the digital circuit, namely the circuit density, power usage, and circuit speed. However, to ensure that the chosen logic gates are ideal against hindering the attackers, an attack algorithm would be used to decipher the camouflaged circuit. The execution time of the algorithm will be analysed, which is what sets this report apart from the other research papers. By analysing the different execution times for different numbers of chosen logic gates, the ideal number of logic gates to be camouflaged can be determined.||URI:||https://hdl.handle.net/10356/138660||Fulltext Permission:||restricted||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Student Reports (FYP/IA/PA/PI)|
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Updated on Nov 23, 2020
Updated on Nov 23, 2020
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