A design of an all-MOS-transistor low-power low-voltage LDO with an embedded voltage reference

Abstract

This report shows the whole process of designing a All-MOS Low Dropout (LDO) with embedded voltage reference. This design will provide a output voltage which is independent of temperature, load current changes, supply voltage et al. The final design contains start-up, PTAT generator, two temperature curvature correction circuits, 3-stage error amplifier and a novel transient response circuit. The whole design process is done under virtuoso tool in Linux system. All simulation and design components are from Global Foundries 0.18 um CMOS technology file. The final design has the minimal input voltage of 0.68V with 656.12V output voltage. The line regulation is -3.22mV/V and load regulation 0.0022 mV/mA. PSRR is 52.36dB. The overall average temperature coefficient is 21.5 ppm/°C. The design is stable under light load and heavy load due to the phase margin is larger than 60 degree. The transient response is good but still can improve. However, the supply current is a little high. In the simulation, high current supply can improve the transient response. Besides, the temperature coefficient can still process to reduce to less than 10 ppm/°C.