Design of a rail-to-rail input-output analog buffer with high PSRR

Abstract

This project presents the design of an analog buffer in 0.18µm CMOS technology. The buffer has the capability to source and sink 100mA load current, and to handle rail to rail input and output voltage swings. The design is implemented with the architecture of a folded cascode operational amplifier with complementary input pairs and Class AB output stage controlled by translinear loops. It can work down from 1.8V to 1.5V in power supply, providing a common mode voltage of half V DD . At the minimum 1.5V supply, the design achieved a 87.8 dB open loop gain with 75.2 degrees phase margin, 60 MHz GBW. The buffer can achieve a signal voltage swing from 50mV to 1.45V, with a total harmonic distortion of -56 dB, and an input-referred noise of about 539 nV/√𝐼𝑧 at 1kHz, while loaded with a 150pF capacitor and a resistive load with 100mA current. This buffer can be applied as a signal buffer for 8Ω loudspeaker.