Design and analysis of low-power 32-bit logarithmic barrel shifter

Abstract

With development of electronic industry, power consumption has become a priority concern for electronic products, therefore lower power design draws increasingly more attention from researchers. And data shift is an important function unit of digital signal processors, which can be achieved by logarithmic barrel shifter. In this dissertation, a 32-bit Logarithmic barrel shifter with logic and arithmetic shift function in both right and left direction is designed in static logic, dynamic logic and sequential logic styles. The simulation and analyze of multiplexer and Logarithmic barrel shifter are both carried out to compare power consumption and delay among different design styles. Meanwhile, the tradeoff between power consumption and delay is discussed through varying supply voltage of circuits. The process of design and simulation is carried out based on Cadence Virtuoso and TSMC’s 40nm technology is employed in this dissertation.