Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/140288
Title: Low power design for approximate adders
Authors: Liu, Ling Li
Keywords: Engineering::Electrical and electronic engineering::Integrated circuits
Engineering::Electrical and electronic engineering::Microelectronics
Issue Date: 2020
Publisher: Nanyang Technological University
Abstract: With the continuous development of integrated circuit manufacturing processes, the issue of power consumption becomes prominent, and the importance of low-power design has become increasingly essential. Different kind of power consumption in CMOS circuits and ways to reduce these consumptions will be discussed in this dissertation. Some approximate algorithms provide a good opportunity for energy-efficient design by reducing accuracy requirements. The full adder (FA), as the most basic arithmetic unit of the IC, is widely used in various operations, its speed, power consumption and area performance directly affect the performance of the entire IC. First, in terms of power consumption, delay, and number of transistors, 6 kinds of precise 1-bit FAs with different implementation and 4 types of approximate adders will be discussed. The PDP (Power-Delay Product) will also be provided. 8-bit FA will be constructed with precise 1-bit FA firstly. Replacing the LSBs (Least Significant Bits) with these 4 approximate adders of the 8-bit FA, simulate and compare their performances with the precise one.
URI: https://hdl.handle.net/10356/140288
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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