Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/140597
Title: Efficient hardware accelerator for NORX authenticated encryption
Authors: Kumar, Sachin
Haj-Yahya, Jawad
Chattopadhyay, Anupam
Keywords: Engineering::Computer science and engineering
Issue Date: 2018
Source: Kumar, S., Haj-Yahya, J., & Chattopadhyay, A. (2018). Efficient hardware accelerator for NORX authenticated encryption. Proceedings of the 2018 IEEE International Symposium on Circuits and Systems (ISCAS). doi:10.1109/ISCAS.2018.8351145
Abstract: Authenticated encryption with associated data (AEAD) plays a significant role in cryptography due to its ability to provide integrity, confidentiality and authenticity at the same time. There is an unceasing demand of high-performance and area-efficient AEAD ciphers due to the emergence of security at the edge of computing fabric, such as, sensors and smartphone devices. Currently, a worldwide contest, titled CAESAR, is being held to decide on a set of AEAD ciphers, which are distinguished by their security, runtime performance, energy-efficiency and low area budget. In this paper, we focus on optimizing the hardware architecture of NORX by applying a pipeline technique. Our pre-layout results using commercial ASIC TSMC 65 technology library show that optimized NORX is 40.81% faster, 18.01% smaller, and improved the throughput per area by 76.9% when compared with state-of-the-art NORX implementation.
URI: https://hdl.handle.net/10356/140597
ISBN: 9781538648810
DOI: 10.1109/ISCAS.2018.8351145
Rights: © 2018 IEEE. All rights reserved.
Fulltext Permission: none
Fulltext Availability: No Fulltext
Appears in Collections:SCSE Conference Papers

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