Reconfigurable digital compute-in-memory circuit designs for solving combinatorial optimization problems

Abstract

The increase in CPU computing speed has become slow in recent years. The main way to improve computer performance is to increase the number of computer cores. For combinatorial optimization problems, the traditional Von Neumann-structured computer can meet the requirements when the number of samples is small, but as the amount of data increases, the number of calculations increases exponentially. In recent years, simulated annealing has been introduced on the market, which maps combinatorial optimization problems into Ising models and finds the optimal solution by annealing. There are currently two types of annealing that have received widespread attention. The advantage of quantum annealing is that the calculation is accurate and the number of calculations is large, but the requirements on the working environment are relatively high, such as the need to work at extremely low temperatures. CMOS annealing by mapping the Ising model to a CMOS circuit has low material requirements and can operate at room temperature. This article mainly introduces quantum annealing and the addition of Compute-in-memory circuits based on previous work, which further enhances the efficiency of the chip and omits the time for data to be transferred between the CPU and the memory. At the same time, through the serial communication and data processing between PC, FPGA, and LED array, this project uses the LED array to display the Compute-In-Memory (CIM) chip calculation results.