Please use this identifier to cite or link to this item:
|Title:||Simulation and optimization of silicon carbide metal oxide semiconductor field effect transistors||Authors:||Zhu,Taolue||Keywords:||Engineering::Electrical and electronic engineering||Issue Date:||2020||Publisher:||Nanyang Technological University||Abstract:||Silicon carbide (SiC), due to its large band gap, high critical breakdown electric field, carrier saturation velocity and thermal conductivity, has been the best choice of material for the fabrication of high power, high temperature and high frequency semiconductor devices. SiC can also be processed to grow a layer of high-quality thermal oxide (SiO2) to form the metal-oxide-semiconductor field effect transistor (MOSFET), which is the most common semiconductor device structure currently used in power devices. As a variation of MOSFET and a promising power device structure, vertically diffused MOS (VDMOS) has the ability of blocking high voltage and conducting large current using an integrated vertically grown structure. Therefore, there is an intense interest in the study of SiC VDMOS device as it combines the best device design with the attractive semiconductor material properties of SiC. In this dissertation, Silvaco, which is a widely used semiconductor device simulation software, is used to simulate the device characteristics of SiC VDMOS power devices. Most physical models used in the mainstream device simulation software are set for the default Si material. This renders the design, simulation and verification of SiC devices challenging, and thus the development and commercialization of SiC power devices is greatly hindered. In this work, with an in-depth understanding of the related electrical characteristics of SiC, adjustments and modifications of the physical models, such as carrier mobility and impact ionization models in Atlas, Silvaco, are carried out for the simulation of 4H-SiC VDMOS. A reliable simulation platform is established by first fitting the simulated device characteristics to those reported experimentally through adjusting the various parameters in the physical models. Using the validated simulation platform, an optimized SiC VDMOS structure is proposed and simulated in terms of the well depth/width and metal material to improve its on resistance (Ron), on current (Ion), breakdown voltage (Vbd). The results obtained are compared against a comparable commercial Cree 1200V power device, it was found the optimized SiC VDMOS has better output characteristics than the former, but due to size issues, it does not have the same commercial value. Keywords: Silvaco, SiC, VDMOS, output characteristics, optimization||URI:||https://hdl.handle.net/10356/141066||Fulltext Permission:||restricted||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Theses|
Updated on Feb 5, 2023
Updated on Feb 5, 2023
Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.