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Title: A distributed control architecture for global system economic operation in autonomous hybrid AC/DC microgrids
Authors: Lin, Pengfeng
Jin, Chi
Xiao, Jianfang
Li, Xiaoqiang
Shi, Donghan
Tang, Yi
Wang, Peng
Keywords: Engineering::Electrical and electronic engineering
Issue Date: 2018
Source: Lin, P., Jin, C., Xiao, J., Li, X., Shi, D., Tang, Y., & Wang, P. (2019). A distributed control architecture for global system economic operation in autonomous hybrid AC/DC microgrids. IEEE Transactions on Smart Grid, 10(3), 2603-2617. doi:10.1109/TSG.2018.2805839
Journal: IEEE Transactions on Smart Grid
Abstract: It is renowned that the entire power system operation cost can be minimized when distributed generators (DGs) have the same incremental costs (ICs). This paper proposes a distributed control architecture for a hybrid ac/dc microgrid (MG) to realize global system economic operation. The architecture consists of two levels. In the first level, the ac frequency-IC (f ac -IC) droop and the dc bus voltage-IC (VdcIC) droop are employed in the ac and dc subgrids, respectively. With the synchronization of f ac and V dc , DG ICs in each subgrid will be equalized. However, the droops will inevitably cause deviations of f ac and V dc . Then a distributed control canonical form (DCCF), which provides a generalized method for f ac and V dc recoveries, is proposed in the second level. The DCCF allows DGs to communicate only with their neighbors, thus alleviating the communication burdens and enhancing the system scalability. Due to the presence of DCCF, f ac and V dc fluctuations, which naturally indicate subgrid loading conditions, are invisible. An original relative loading index (RLI) is proposed to extract the hidden loading condition of each subgrid even thoughfac and V dc are clamped as constants. By using RLI, the power reference of the bidirectional interlinking converter can be easily defined. All DG ICs the hybrid MG converge to the same value in the steady state. The feasibility and effectiveness of the proposed control architecture are verified by simulations and RT-LAB hardware in loop tests.
ISSN: 1949-3053
DOI: 10.1109/TSG.2018.2805839
Rights: © 2018 IEEE. All rights reserved.
Fulltext Permission: none
Fulltext Availability: No Fulltext
Appears in Collections:EEE Journal Articles

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