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|Title:||Design and implementation of fourth arm for elimination of bearing current in NPC-MLI-Fed induction motor drive||Authors:||Bharatiraja, C.
Chelliah, T. R.
Munda, J. L.
Maswood, Ali Iftekhar
|Keywords:||Engineering::Electrical and electronic engineering||Issue Date:||2018||Source:||Bharatiraja, C., Selvaraj, R., Chelliah, T. R., Munda, J. L., Mohd Tariq., & Maswood, A. I. (2018). Design and implementation of fourth arm for elimination of bearing current in NPC-MLI-Fed induction motor drive. IEEE Transactions on Industry Applications, 54(1), 745 - 754. doi:10.1109/TIA.2017.2759204||Journal:||IEEE Transactions on Industry Applications||Abstract:||The exploration result of an increase in power electronics converter-based variable-speed drives for industrial applications reveals the impact of inverter-induced bearing current on the prevailing electric machine failure. The bearing current associated with drive systems is concerned about operating frequencies of the solid-state semiconductor switches, which may cause the electrostatic charge between stator and rotor, which eventually causes damage to windings and bearings. The various techniques comprised in the literature to suppress bearing currents are filter design, switching redundancy, common-mode circuitry, isolated grounding scheme, and grounding the motor shaft. From the literature, the pulse-width modulation inverter-injected common-mode voltage (CMV) is the main source of common-mode current, which causes the bearing current. Hence, the elimination of CMV paves the way for eliminating bearing current of the machine. This paper presents an innovative solution to suppress bearing currents by aiding a fourth arm circuitry to acquire near to zero potential (zero CMV) at machine neutral point. All the proposed circuitry and algorithm are simulated using MATLAB/Simulink and validation is done through a 2.5-kW neutral-point-clamped-multilevel inverter laboratory prototype using a Xilinx family SPARTAN-III-3A XC3SD1800A-FG676 digital signal processor-field programmable gate array board.||URI:||https://hdl.handle.net/10356/141346||ISSN:||0093-9994||DOI:||10.1109/TIA.2017.2759204||Rights:||© 2017 IEEE. All rights reserved.||Fulltext Permission:||none||Fulltext Availability:||No Fulltext|
|Appears in Collections:||EEE Journal Articles|
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