Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/141472
Title: Inducing alternating nanoscale rectification in a dielectric material for bidirectional-trigger artificial synapses
Authors: Berco, Dan
Ang, Diing Shenp
Keywords: Engineering::Electrical and electronic engineering
Issue Date: 2019
Source: Berco, D., & Ang, D. A. (2019). Inducing alternating nanoscale rectification in a dielectric material for bidirectional-trigger artificial synapses. Journal of Vacuum Science and Technology B: Nanotechnology and Microelectronics, 37(6), 061806-. doi:10.1116/1.5123665
Journal: Journal of Vacuum Science and Technology B: Nanotechnology and Microelectronics
Abstract: Nanoionic device-based artificial neural networks that consume little power and hold a potential for enormous densities still fall behind the capabilities of software algorithms running on traditional von Neumann machines. In addition, despite many publications showing multilevel parametric capabilities associated with these devices, a real-world nonvolatile memory application that maximizes their potential density is yet to be realized. One reason may be due to their limited functional mode as an analog passive element that is crippled by large interdevice variations. This work demonstrates that the nanoscale stoichiometry in transition metal oxides can be triggered to form asymmetric cationlike vacancy distributions that yield dynamically toggled current rectifying properties. In this manner, a rectifying device operated as an artificial synapse is capable of switching between excitatory and inhibitory modes, dissipating ∼20 fJ/switching event. This complementary functionality (in a similar manner to CMOS transistors) adds a whole new degree of freedom to the design of neuromorphic computing platforms. Moreover, the entire spectrum of nonvolatile states derived from different cation distributions (positive-rectifying, negative-rectifying, conductive, and insulating) may be considered as a mutually exclusive and interchangeable basis set for robust multilevel memory implementation that overcomes the issues associated with large process and device related parametric distributions.
URI: https://hdl.handle.net/10356/141472
ISSN: 2166-2746
DOI: 10.1116/1.5123665
Rights: © 2019 The Author(s). All rights reserved. This paper was published by the AVS in Journal of Vacuum Science and Technology B: Nanotechnology and Microelectronics and is made available with permission of The Author(s).
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Journal Articles

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