Please use this identifier to cite or link to this item:
Title: A high resolution : low power GRO-TDC for digital frac-N Σ∆ frequency synthesizers
Authors: Seah, Bryan Yun Da
Keywords: Engineering::Electrical and electronic engineering
Issue Date: 2020
Publisher: Nanyang Technological University
Project: A2167-191
Abstract: This report presents a novel Simulink model of the All Digital Phase Locked Loop (ADPLL), which can be used in future developments if one wishes to design an ADPLL for a particular application. Also, a Gated Ring Oscillator-TDC was designed in 40nm CMOS, achieving a effective resolution of 0.73ps @ 1MHz PLL Loop Bandwidth.
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Student Reports (FYP/IA/PA/PI)

Files in This Item:
File Description SizeFormat 
  Restricted Access
2.79 MBAdobe PDFView/Open

Page view(s)

checked on Sep 30, 2020


checked on Sep 30, 2020

Google ScholarTM


Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.