A high resolution : low power GRO-TDC for digital frac-N Σ∆ frequency synthesizers

Abstract

This report presents a novel Simulink model of the All Digital Phase Locked Loop (ADPLL), which can be used in future developments if one wishes to design an ADPLL for a particular application. Also, a Gated Ring Oscillator-TDC was designed in 40nm CMOS, achieving a effective resolution of 0.73ps @ 1MHz PLL Loop Bandwidth.