Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/141919
Title: 16-bit low power CMOS multiplier IC design
Authors: Hu, Hang
Keywords: Engineering::Electrical and electronic engineering
Issue Date: 2020
Publisher: Nanyang Technological University
Project: P2012-181
Abstract: As technology evolves, FPGA has been used in every aspect of our lives, therefore, IC design is highly demanded in the market. Adders and multipliers are the fundamental arithmetic operators in IC design. To compare how efficient a multiplier is designed, low power consumption is one of the key points we are looking at. This project aims to develop a multiplier using Verilog HDL, with different approaches (sequential multiplier and Braun multiplier). The developed multiplier is then evaluated and simulated to compare the power consumption.
URI: https://hdl.handle.net/10356/141919
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Student Reports (FYP/IA/PA/PI)

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