16-bit low power CMOS multiplier IC design

Abstract

As technology evolves, FPGA has been used in every aspect of our lives, therefore, IC design is highly demanded in the market. Adders and multipliers are the fundamental arithmetic operators in IC design. To compare how efficient a multiplier is designed, low power consumption is one of the key points we are looking at. This project aims to develop a multiplier using Verilog HDL, with different approaches (sequential multiplier and Braun multiplier). The developed multiplier is then evaluated and simulated to compare the power consumption.