Please use this identifier to cite or link to this item:
Title: A high-throughput VLSI architecture for real-time full-HD gradient guided image filter
Authors: Wu, Lei
Jong, Ching Chuen
Keywords: Engineering::Electrical and electronic engineering
Issue Date: 2018
Source: Wu, L., & Jong, C. C. (2019). A high-throughput VLSI architecture for real-time full-HD gradient guided image filter. IEEE Transactions on Circuits and Systems for Video Technology, 29(6), 1868-1877. doi:10.1109/TCSVT.2018.2852336
Journal: IEEE Transactions on Circuits and Systems for Video Technology
Abstract: Guided image filtering has been applied widely in recent years as a solution to the ever-increasing demand of high-performance filtering, especially for real-time image/video processing. The lately proposed gradient domain guided image filter (GDGIF) is one of the typical works focusing on improving the quality of the filtering result of the original guided image filter (GIF), dealing with the halo-artifacts problem for edge-preserving smoothing. However, due to the involvement of global pixel values in the computation, high computation complexity, and additional complex operation, there is no existing VLSI design for the gradient guided filter. This paper presents a high-throughput VLSI architecture for real-time full-HD (1920× 1080) GDGIF. Four techniques are used in the newly proposed design to reduce the computation complexity and increase the processing throughput. First, a pre-processing stage is introduced to address the problem of global parameters required in the GDGIF. Second, multi-scale down-samplings are adopted for reducing circuit size and processing time. Then, a parallel structure operated at a higher frequency is used at the output stage to restore the full image size and to achieve high throughput at the same time. At last, approximated computation is introduced to eliminate speed bottleneck by simplifying the complex exponentiation operation. Based on the STM 65-nm CMOS technology, the implementation results show that the proposed architecture is able to support full-HD image filtering at a throughput above 75 frame/s, with a design area of 586314 μm2 and a power consumption of 18.5 mW.
ISSN: 1051-8215
DOI: 10.1109/TCSVT.2018.2852336
Rights: © 2018 IEEE. All rights reserved.
Fulltext Permission: none
Fulltext Availability: No Fulltext
Appears in Collections:EEE Journal Articles

Citations 50

Updated on Jan 29, 2023

Web of ScienceTM
Citations 20

Updated on Jan 31, 2023

Page view(s)

Updated on Feb 5, 2023

Google ScholarTM




Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.