Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/142271
Title: Reliability study of copper wire bonding and through silicon via
Authors: Chan, Marvin Jiawei
Keywords: Engineering::Electrical and electronic engineering::Electronic packaging
Engineering::Electrical and electronic engineering::Microelectronics
Issue Date: 2020
Publisher: Nanyang Technological University
Source: Chan, M. J. (2020). Reliability study of copper wire bonding and through silicon via. Doctoral thesis, Nanyang Technological University, Singapore.
Abstract: Interconnects are necessary for the electrical connection of an integrated circuits (IC). Therefore, its quality and reliability are vitally important to ensure that a device is working as it is intendedly designed. The continued scaling of devices and the desire for higher functionality and capability has led to the exploration for new interconnect technologies and new materials. One of the most widely used interconnect method by the IC manufacturing industry is wire bonding. In order to remain competitive as one of the key interconnect technologies in the market, copper (Cu) wires have recently been adopted to replace gold (Au) wires due to its lower costs and more desirable material properties. Current industrial practices to evaluate wire bond quality after the assembly and packaging process are either done destructively which may result in loss of critical information, or non-destructively which are limited by resolution, cost and time. In this work, the quality of copper wire bond is being evaluated after temperature cycling (TC) stress, by electrical means that is non-destructive, fast and accurate. This makes it suitable for use in the production line for wire bond quality evaluation. Experimental results showed that there is a good correlation with conventional wire assessment methods. Furthermore the electrical method is sensitive enough to screen out degraded wires that conventional methods are unable to identify. Apart from Cu wire bonding, through silicon via (TSV) technology has also in recent years, been actively pursued and has become one of the key enablers for three dimensional (3D) IC. It allows for vertical interconnection of dies, which not only overcome spatial limitations, but also enables the possibility of heterogeneous integration to enhance functionality and performance. Although there are several advantages that Cu TSV interconnect technology can offer, there are also several reliability concerns that have not been well addressed which requires further study. Reliability stress test such as TC and high temperature storage life (HTSL) were performed on various TSV structures. Degradation of the barrier liner resulting in the migration of Cu into the dielectric liner can be observed and detected from the C-V characteristics curve and verified with physical failure analysis. Furthermore, by applying an appropriate electrical field across the dielectric layer, the control of Cu ions transport can be monitored. The influence on the presence of Cu on the leakage current conduction mechanism and time dependent dielectric breakdown (TDDB) is discussed.
URI: https://hdl.handle.net/10356/142271
DOI: 10.32657/10356/142271
Rights: This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License (CC BY-NC 4.0).
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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