Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/142374
Full metadata record
DC FieldValueLanguage
dc.contributor.authorBalasubramanian, Padmanabhanen_US
dc.contributor.authorMaskell, Douglas Leslieen_US
dc.date.accessioned2020-06-19T07:51:08Z-
dc.date.available2020-06-19T07:51:08Z-
dc.date.issued2019-
dc.identifier.citationBalasubramanian, P., & Maskell, D. L. (2019). Indicating asynchronous array multipliers. International Journal of Circuits, Systems and Signal Processing, 13, 464-471.en_US
dc.identifier.issn1998-4464en_US
dc.identifier.urihttps://naun.org/cms.action?id=19907-
dc.identifier.urihttps://hdl.handle.net/10356/142374-
dc.description.abstractMultiplication is an important arithmetic operation that is frequently encountered in microprocessing and digital signal processing applications, and multiplication is physically realized using a multiplier. This paper discusses the physical implementation of many indicating asynchronous array multipliers, which are inherently elastic and modular and are robust to timing, process and parametric variations. We consider the physical realization of many indicating asynchronous array multipliers using a 32/28nm CMOS technology. The weak-indication array multipliers comprise strong-indication or weak-indication full adders, and strong-indication 2-input AND functions to realize the partial products. The multipliers were synthesized in a semi-custom ASIC design style using standard library cells including a custom-designed 2-input C-element. 4x4 and 8x8 multiplication operations were considered for the physical implementations. The 4-phase return-to-zero (RTZ) and the 4-phase return-to-one (RTO) handshake protocols were utilized for data communication, and the delay-insensitive dual-rail code was used for data encoding. Among several weak-indication array multipliers, a weak-indication array multiplier utilizing a biased weak-indication full adder and the strong-indication 2-input AND function is found to have reduced cycle time and power-cycle time product with respect to RTZ and RTO handshaking for 4x4 and 8x8 multiplications. Further, the 4-phase RTO handshaking is found to be preferable to the 4-phase RTZ handshaking for achieving enhanced optimizations of the design metrics.en_US
dc.description.sponsorshipMOE (Min. of Education, S’pore)en_US
dc.language.isoenen_US
dc.relation.ispartofInternational Journal of Circuits, Systems and Signal Processingen_US
dc.rights© 2019 The Author(s) (published by NAUN). This is an open-access article distributed under the terms of the Creative Commons Attribution License.en_US
dc.subjectEngineering::Computer science and engineeringen_US
dc.titleIndicating asynchronous array multipliersen_US
dc.typeJournal Articleen
dc.contributor.schoolSchool of Computer Science and Engineeringen_US
dc.description.versionPublished versionen_US
dc.identifier.volume13en_US
dc.identifier.spage464en_US
dc.identifier.epage471en_US
dc.subject.keywordsArithmetic Circuitsen_US
dc.subject.keywordsAsynchronous Circuitsen_US
item.grantfulltextopen-
item.fulltextWith Fulltext-
Appears in Collections:SCSE Journal Articles
Files in This Item:
File Description SizeFormat 
Indicating asynchronous array multipliers.pdf162.81 kBAdobe PDFView/Open

Page view(s)

58
Updated on Jan 29, 2023

Download(s)

14
Updated on Jan 29, 2023

Google ScholarTM

Check

Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.