Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/142504
Title: A hardware-efficient synchronization in L-DACS1 for aeronautical communications
Authors: Pham, Thinh Hung
Prasad, Vinod A.
Madhukumar, A. S.
Keywords: Engineering::Computer science and engineering
Issue Date: 2018
Source: Pham, T. H., Prasad, V. A., & Madhukumar, A. S. (2018). A hardware-efficient synchronization in L-DACS1 for aeronautical communications. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 26(5), 924-932. doi:10.1109/TVLSI.2018.2789467
Journal: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Abstract: L -band digital aeronautical communication system type-1 (L-DACS1) is an emerging standard that aims at enhancing air traffic management by transitioning the traditional analog aeronautical communication systems to the superior and highly efficient digital domain. L-DACS1 employs modern and efficient orthogonal frequency-division multiplexing (OFDM) modulation technique to achieve more efficient and higher data rate in comparison to the existing aeronautical communication systems. However, the performance of OFDM systems is very sensitive to synchronization errors such as symbol timing offset (STO) and carrier frequency offset (CFO). STO and CFO estimations are extremely important for maintaining orthogonality among the subcarriers for the retrieval of information. This paper proposes a novel efficient hardware synchronizer for L-DACS1 systems that offers robust performance at low power and low hardware resource usage. Monte Carlo simulations show that the proposed synchronization algorithm provides accurate STO estimation as well as fractional CFO estimation. Implementation of the proposed synchronizer on a widely used field-programmable gate array (FPGA) (Xilinx xc7z020clg484-1) results in a very low hardware usage which consumed 6.5%, 3.7%, and 6.4% of the total number of lookup tables, flip-flops, and digital signal processing blocks, respectively. The dynamic power of the proposed synchronizer is below 1 mW.
URI: https://hdl.handle.net/10356/142504
ISSN: 1063-8210
DOI: 10.1109/TVLSI.2018.2789467
Rights: © 2018 IEEE. All rights reserved.
Fulltext Permission: none
Fulltext Availability: No Fulltext
Appears in Collections:SCSE Journal Articles

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