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|Title:||An area-efficient 128-channel spike sorting processor for real-time neural recording with 0.175 μ W/channel in 65-nm CMOS||Authors:||Do, Anh Tuan
Seyed Mohammad Ali Zeinolabedin
Kim, Tony Tae-Hyoung
|Keywords:||Engineering::Electrical and electronic engineering||Issue Date:||2018||Source:||Do, A. T., Seyed Mohammad Ali Zeinolabedin, Jeon, D., Sylvester, D., & Kim, T. T.-H. (2019). An area-efficient 128-channel spike sorting processor for real-time neural recording with 0.175 μ W/channel in 65-nm CMOS. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 27(1), 126-137. doi:10.1109/TVLSI.2018.2875934||Journal:||IEEE Transactions on Very Large Scale Integration (VLSI) Systems||Abstract:||This paper presents a power- and area-efficient spike sorting processor (SSP) for real-time neural recordings. The proposed SSP includes novel detection, feature extraction, and improved K-means algorithms for better clustering accuracy, online clustering performance, and lower power and smaller area per channel. Time-multiplexed registers are utilized in the detector for dynamic power reduction. Finally, an ultralow-voltage 8T static random access memory (SRAM) is developed to reduce area and leakage consumption when compared to D flip-flop -based memory. The proposed SSP, fabricated in 65-nm CMOS process technology, consumes only 0.175 μW/channel when processing 128 input channels at 3.2 MHz and 0.54 V, which is the lowest among the compared state-of-the-art SSPs. The proposed SSP also occupies 0.003 mm2/channel, which allows 333 channels/mm2.||URI:||https://hdl.handle.net/10356/142509||ISSN:||1063-8210||DOI:||10.1109/TVLSI.2018.2875934||Rights:||© 2018 IEEE. All rights reserved.||Fulltext Permission:||none||Fulltext Availability:||No Fulltext|
|Appears in Collections:||EEE Journal Articles|
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