Please use this identifier to cite or link to this item:
|Title:||A high-speed 2-bit/cycle SAR ADC with time-domain quantization||Authors:||Qiu, Lei
|Keywords:||Engineering::Electrical and electronic engineering||Issue Date:||2018||Source:||Qiu, L., Yang, C., Wang, K., & Zheng, Y. (2018). A high-speed 2-bit/cycle SAR ADC with time-domain quantization. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 26(10), 2175-2179. doi:10.1109/TVLSI.2018.2837030||Journal:||IEEE Transactions on Very Large Scale Integration (VLSI) Systems||Abstract:||This brief presents a 2-bit/cycle successive approximation register (SAR) analog-to-digital converter (ADC) with time-domain quantization, which only needs one capacitive digital-to-analog converter (DAC) array. A duplicated dynamic comparator is adopted to generate the time references. To quantize the time value, a dynamic latch-based high precision time-domain comparator is proposed. Moreover, a redundancy technique is utilized to overcome the effect of nonideal factors, such as incomplete DAC settling, reference scale mismatch, and offset of comparators. A design example of 9-bit 700 MS/s SAR ADC in 65-nm CMOS technology is presented. Simulation results show that with a differential 600-mVp-p input, the spurious free dynamic range at Nyquist input is above 65 dB. The simulated effective number of bit is up to 8.3 bits at 10-MHz input with the presence of noise and mismatches calibration.||URI:||https://hdl.handle.net/10356/142511||ISSN:||1063-8210||DOI:||10.1109/TVLSI.2018.2837030||Rights:||© 2018 IEEE. All rights reserved.||Fulltext Permission:||none||Fulltext Availability:||No Fulltext|
|Appears in Collections:||EEE Journal Articles|
Updated on Mar 10, 2021
Updated on Mar 7, 2021
Updated on Jun 15, 2021
Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.