Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/142511
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dc.contributor.authorQiu, Leien_US
dc.contributor.authorYang, Chuanshien_US
dc.contributor.authorWang, Kepingen_US
dc.contributor.authorZheng, Yuanjinen_US
dc.date.accessioned2020-06-23T04:20:26Z-
dc.date.available2020-06-23T04:20:26Z-
dc.date.issued2018-
dc.identifier.citationQiu, L., Yang, C., Wang, K., & Zheng, Y. (2018). A high-speed 2-bit/cycle SAR ADC with time-domain quantization. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 26(10), 2175-2179. doi:10.1109/TVLSI.2018.2837030en_US
dc.identifier.issn1063-8210en_US
dc.identifier.urihttps://hdl.handle.net/10356/142511-
dc.description.abstractThis brief presents a 2-bit/cycle successive approximation register (SAR) analog-to-digital converter (ADC) with time-domain quantization, which only needs one capacitive digital-to-analog converter (DAC) array. A duplicated dynamic comparator is adopted to generate the time references. To quantize the time value, a dynamic latch-based high precision time-domain comparator is proposed. Moreover, a redundancy technique is utilized to overcome the effect of nonideal factors, such as incomplete DAC settling, reference scale mismatch, and offset of comparators. A design example of 9-bit 700 MS/s SAR ADC in 65-nm CMOS technology is presented. Simulation results show that with a differential 600-mVp-p input, the spurious free dynamic range at Nyquist input is above 65 dB. The simulated effective number of bit is up to 8.3 bits at 10-MHz input with the presence of noise and mismatches calibration.en_US
dc.language.isoenen_US
dc.relation.ispartofIEEE Transactions on Very Large Scale Integration (VLSI) Systemsen_US
dc.rights© 2018 IEEE. All rights reserved.en_US
dc.subjectEngineering::Electrical and electronic engineeringen_US
dc.titleA high-speed 2-bit/cycle SAR ADC with time-domain quantizationen_US
dc.typeJournal Articleen
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.identifier.doi10.1109/TVLSI.2018.2837030-
dc.identifier.scopus2-s2.0-85048188971-
dc.identifier.issue10en_US
dc.identifier.volume26en_US
dc.identifier.spage2175en_US
dc.identifier.epage2179en_US
dc.subject.keywords2 Bit/cycleen_US
dc.subject.keywordsAnalog-to-digital Converter (ADC)en_US
item.grantfulltextnone-
item.fulltextNo Fulltext-
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