Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/142579
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dc.contributor.authorLiu, Beien_US
dc.date.accessioned2020-06-25T00:35:48Z-
dc.date.available2020-06-25T00:35:48Z-
dc.date.issued2020-
dc.identifier.citationLiu, B. (2020). Design of transmitter front-end for WLAN 802.11ax application. Doctoral thesis, Nanyang Technological University, Singapore.en_US
dc.identifier.urihttps://hdl.handle.net/10356/142579-
dc.description.abstractAs the successor to current IEEE 802.11ac, the emerging IEEE 802.11ax will increase the efficiency of wireless local area network (WLAN) networks, especially in the high-density WLAN deployment scenario, and the data rate is expected to reach 10 Gbps. Carrier aggregation (CA) will be a key feature of 802.11ax system to boost data rate. Voltage-controlled oscillator (VCO) pulling and crosstalk between RF channels are two main problems related to carrier aggregation due to the inevitable coupling and leakage between different signal transmitting channels in one complementary metal-oxide silicon (CMOS) chip, which introduce severe impacts on adjacent channel leakage ratio (ACLR) and error vector magnitude (EVM). To address these two problems, high isolation between signal transmitting channels is required, but may not be realizable in some practical cases due to the constraint of layout. Firstly, this thesis proposes a new transmitter architecture using parallel direct-conversion and double-conversion configuration, which can address the problems of crosstalk and VCO pulling simultaneously without large physical isolation. Based on the proposed transmitter architecture, a transmitter front-end supporting two-carriers aggregation for 5-GHz WLAN 802.11ax application is designed and implemented in TSMC 40-nm CMOS technology. For contiguous intra-band carrier aggregation with two VHT80, MCS9 signals (80-MHz bandwidth, 256-quadrature amplitude modulation (QAM) and 11.25-dB peak-to-average power ratio (PAPR)), the transmitter front-end delivers an average output power of 5.3+4.8 dBm for two carriers with the EVM ≤ -32 dB, and the EVM can reach -36.1 dB. 802.11ax’s systems are designed to operate in the existing 2.4-GHz and 5-GHz (4.9-5.9 GHz) spectrums, requiring a 2.4/5-GHz dual-band transmitter front-end. A single transmitter supporting reconfigurable 2.4/5-GHz dual-band operation is superior to the dual-band architecture using two transmitters channels in terms of lower cost. Currently, no reconfigurable dual-band transmitter using only one transmitting channel is available in academia and industry. Therefore, another effort of this thesis is to design such a reconfigurable 2.4/5-GHz dual-band transmitter front-end for 802.11ax application. As a core block in a transmitter, the power amplifier (PA) should also operate in the 2.4- and 5-GHz bands. This thesis presents a new design methodology of the reconfigurable dual-band output matching network to extract high passive efficiency. A 2.4/5-GHz dual-band PA is designed to validate the proposed matching methodology. In the 2.4-GHz and 5-GHz WLAN bands, the PA achieves a saturated output power (Psat) of 23 dBm and 21.9-22.4 dBm with power-added efficiency (PAE) of 27% and 24.2-28.2%, respectively. Then, a transmitter front-end supporting the 2.4/5-GHz dual-band operation for WLAN 802.11ax application is designed. The measurement results verify that the transmitter front-end can support the 802.11ax signal with 1024-QAM modulation both in the 2.4- and 5-GHz bands. Since only one RF channel is used, the proposed transmitter front-end has the advantages of simpler design, smaller chip size and lower cost, in comparison with other state-of-the-art dual-band WLAN transmitters.en_US
dc.language.isoenen_US
dc.publisherNanyang Technological Universityen_US
dc.rightsThis work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License (CC BY-NC 4.0).en_US
dc.subjectEngineering::Electrical and electronic engineeringen_US
dc.titleDesign of transmitter front-end for WLAN 802.11ax applicationen_US
dc.typeThesis-Doctor of Philosophyen_US
dc.contributor.supervisorBoon Chirn Chyeen_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.description.degreeDoctor of Philosophyen_US
dc.contributor.researchCentre for Integrated Circuits and Systemsen_US
dc.identifier.doi10.32657/10356/142579-
dc.contributor.supervisoremailECCBoon@ntu.edu.sgen_US
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