Low power CMOS clocked storage elements

Abstract

Modern Systems-on-chips (SoCs) pack tens of millions of gates in a minuscule area which has resulted in the power consumption of chips reaching their fundamental limits. Clocked Storage Elements (CSEs) serve the purpose of synchronizing the logic across the entire chip and make sure that correct functionality is maintained. Thus, the CSEs, along with the clock are at the heart of any modern digital system. This dissertation aims to quantitatively analyze and compare between 5 different classes of flip-flops - the conventional flip-flops, TSPC-based flip-flops, differential flip-flops, pulse-triggered flip-flops and dual edge-triggered flip-flops. Performance metrics that are compared include the power-delay product (PDP), setup and hold times as well as maximum load driving capability. The power performance of the flip-flops for a variety of input patterns is also calculated. Finally, the results are presented.