Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/142931
Title: Threshold-guided design and optimization for Harris corner detector architecture
Authors: Jasani, Bhavan Ashwin
Lam, Siew-Kei
Meher, Pramod Kumar
Wu, Meiqing
Keywords: Engineering::Computer science and engineering
Issue Date: 2017
Source: Jasani, B. A., Lam, S.-K., Meher, P. K., & Wu, M. (2018). Threshold-guided design and optimization for Harris corner detector architecture. IEEE Transactions on Circuits and Systems for Video Technology, 28(12), 3516-3526. doi:10.1109/TCSVT.2017.2757998
Journal: IEEE Transactions on Circuits and Systems for Video Technology
Abstract: High-speed corner detection is an essential step in many real-time computer vision applications, e.g., object recognition, motion analysis, and stereo matching. Hardware implementation of corner detection algorithms, such as the Harris corner detector (HCD) has become a viable solution for meeting real-time requirements of the applications. A major challenge lies in the design of power, energy and area efficient architectures that can be deployed in tightly constrained embedded systems while still meeting real-time requirements. In this paper, we proposed a bit-width optimization strategy for designing hardware-efficient HCD that exploits the thresholding step in the algorithm to determine interest points from the corner responses. The proposed strategy relies on the threshold as a guide to truncate the bit-widths of the operators at various stages of the HCD pipeline with only marginal loss of accuracy. Synthesis results based on 65-nm CMOS technology show that the proposed strategy leads to power-delay reduction of 35.2%, and area reduction of 35.4% over the baseline implementation. In addition, through careful retiming, the proposed implementation achieves over 2.2 times increase in maximum frequency while achieving an area reduction of 35.1% and power-delay reduction of 35.7% over the baseline implementation. Finally, we performed repeatability tests to show that the optimized HCD architecture achieves comparable accuracy with the baseline implementation (average decrease of repeatability is less than 0.6%).
URI: https://hdl.handle.net/10356/142931
ISSN: 1051-8215
DOI: 10.1109/TCSVT.2017.2757998
Schools: School of Computer Science and Engineering 
Organisations: Hardware and Embedded Systems Laboratory
Rights: © 2017 IEEE. All rights reserved.
Fulltext Permission: none
Fulltext Availability: No Fulltext
Appears in Collections:SCSE Journal Articles

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