Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/142972
Title: Looting the LUTs : FPGA optimization of AES and AES-like ciphers for authenticated encryption
Authors: Khairallah, Mustafa
Chattopadhyay, Anupam
Peyrin, Thomas
Keywords: Engineering::Computer science and engineering
Issue Date: 2017
Source: Khairallah, M., Chattopadhyay, A., & Peyrin, T. (2017). Looting the LUTs : FPGA optimization of AES and AES-like ciphers for authenticated encryption. Proceedings of the 18th International Conference on Cryptology in India 2017, 282-301. doi:10.1007/978-3-319-71667-1_15
Abstract: In this paper, we investigate the efficiency of FPGA implementations of AES and AES-like ciphers, specially in the context of authenticated encryption. We consider the encryption/decryption and the authentication/verification structures of OCB-like modes (like OTR or SCT modes). Their main advantage is that they are fully parallelisable. While this feature has already been used to increase the throughput/performance of hardware implementations, it is usually overlooked while comparing different ciphers. We show how to use it with zero area overhead, leading to a very significant efficiency gain. Additionally, we show that using FPGA technology mapping instead of logic optimization, the area of both the linear and non linear parts of the round function of several AES-like primitives can be reduced, without affecting the run-time performance. We provide the implementation results of two multi-stream implementations of both the LED and AES block ciphers. The AES implementation in this paper achieves an efficiency of 38 Mbps/slice, which is the most efficient implementation in literature, to the best of our knowledge. For LED, achieves 2.5 Mbps/slice on Spartan 3 FPGA, which is 2.57x better than the previous implementation. Besides, we use our new techniques to optimize the FPGA implementation of the CAESAR candidate Deoxys-I in both the encryption only and encryption/decryption settings. Finally, we show that the efficiency gains of the proposed techniques extend to other technologies, such as ASIC, as well.
URI: https://hdl.handle.net/10356/142972
ISBN: 978-3-319-71666-4
DOI: 10.1007/978-3-319-71667-1_15
Rights: © 2017 Springer International Publishing AG. All rights reserved.
Fulltext Permission: none
Fulltext Availability: No Fulltext
Appears in Collections:SPMS Conference Papers

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