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Title: Lightweight secure-boot architecture for RISC-V System-on-Chip
Authors: Haj-Yahya, Jawad
Wong, Ming Ming
Pudi, Vikramkumar
Bhasin, Shivam
Chattopadhyay, Anupam
Keywords: Engineering::Computer science and engineering
Issue Date: 2019
Source: Haj-Yahya, J., Wong, M. M., Pudi, V., Bhasin, S., & Chattopadhyay, A. (2019). Lightweight secure-boot architecture for RISC-V System-on-Chip. Proceedings of the 20th International Symposium on Quality Electronic Design (ISQED), 216-223. doi:10.1109/ISQED.2019.8697657
metadata.dc.contributor.conference: 20th International Symposium on Quality Electronic Design (ISQED)
Abstract: Securing thousands of connected, resource-constrained computing devices is a major challenge nowadays. Adding to the challenge, third party service providers need regular access to the system. To ensure the integrity of the system and authenticity of the software vendor, secure boot is supported by several commercial processors. However, the existing solutions are either complex, or have been compromised by determined attackers. In this scenario, open-source secure computing architectures are poised to play an important role for designers and white hat attackers. In this manuscript, we propose a lightweight hardware-based secure boot architecture. The architecture uses efficient implementation of Elliptic Curve Digital Signature Algorithm (ECDSA), Secure Hash Algorithm 3 (SHA3) hashing algorithm and Direct Memory Access (DMA). In addition, the architecture includes Key Management Unit, which incorporates an optimized Physical Unclonable Function (PUF) for providing keys to the security blocks of the System on Chip (SoC), among which, secure boot and remote attestation. We demonstrated the framework on RISC-V based SoC. Detailed analysis of performance and security for the platform is presented.
ISBN: 978-1-7281-0393-8
DOI: 10.1109/ISQED.2019.8697657
Schools: School of Computer Science and Engineering 
Organisations: Institute of Microelectronics, A*STAR
Rights: © 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at:
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:SCSE Conference Papers

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