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Title: Hardware efficient approximate adder design
Authors: Balasubramanian, Padmanabhan
Maskell, Douglas
Keywords: Engineering::Computer science and engineering::Hardware
Engineering::Electrical and electronic engineering::Integrated circuits
Issue Date: 2018
Source: Balasubramanian, P., & Maskell, D. (2018). Hardware efficient approximate adder design. 2018 IEEE Region 10 Conference (TENCON), 0806-0810. doi:10.1109/TENCON.2018.8650127
Project: MOE2017-T2-1-002 
Conference: 2018 IEEE Region 10 Conference (TENCON)
Abstract: This paper presents a new approximate adder architecture which when implemented on an FPGA consumes fewer logic resources compared to accurate adders of similar size and can achieve higher or comparable operating frequencies. For 32-bit addition, our approximate adder achieves a 25% reduction in the number of LUTs utilized compared to the accurate adder with no compromise on the speed performance. For 64-bit addition, our approximate adder achieves a 24% improvement in the maximum operating frequency, and a 25% reduction in the number of LUTs utilized compared to the accurate adder (post place and route on a Virtex-7 FPGA device). We also make comparisons with the FPGA-based implementations of some well-known gate-level approximate adders, and further provide insights into the error characteristics showing that the proposed approximate adder has a reduced error range.
ISBN: 978-1-5386-5457-6
DOI: 10.1109/TENCON.2018.8650127
Schools: School of Computer Science and Engineering 
Rights: © 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:SCSE Conference Papers

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