Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/143971
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dc.contributor.authorBalasubramanian, Padmanabhanen_US
dc.contributor.authorMaskell, Douglasen_US
dc.date.accessioned2020-10-06T00:56:02Z-
dc.date.available2020-10-06T00:56:02Z-
dc.date.issued2018-
dc.identifier.citationBalasubramanian, P., & Maskell, D. (2018). Hardware efficient approximate adder design. 2018 IEEE Region 10 Conference (TENCON), 0806-0810. doi:10.1109/TENCON.2018.8650127en_US
dc.identifier.isbn978-1-5386-5457-6-
dc.identifier.urihttps://hdl.handle.net/10356/143971-
dc.description.abstractThis paper presents a new approximate adder architecture which when implemented on an FPGA consumes fewer logic resources compared to accurate adders of similar size and can achieve higher or comparable operating frequencies. For 32-bit addition, our approximate adder achieves a 25% reduction in the number of LUTs utilized compared to the accurate adder with no compromise on the speed performance. For 64-bit addition, our approximate adder achieves a 24% improvement in the maximum operating frequency, and a 25% reduction in the number of LUTs utilized compared to the accurate adder (post place and route on a Virtex-7 FPGA device). We also make comparisons with the FPGA-based implementations of some well-known gate-level approximate adders, and further provide insights into the error characteristics showing that the proposed approximate adder has a reduced error range.en_US
dc.description.sponsorshipMinistry of Education (MOE)en_US
dc.language.isoenen_US
dc.relationMOE2017-T2-1-002en_US
dc.relationRG132/16en_US
dc.rights© 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at https://doi.org/10.1109/TENCON.2018.8650127en_US
dc.subjectEngineering::Computer science and engineering::Hardwareen_US
dc.subjectEngineering::Electrical and electronic engineering::Integrated circuitsen_US
dc.titleHardware efficient approximate adder designen_US
dc.typeConference Paperen
dc.contributor.schoolSchool of Computer Science and Engineeringen_US
dc.contributor.conference2018 IEEE Region 10 Conference (TENCON)en_US
dc.identifier.doi10.1109/TENCON.2018.8650127-
dc.description.versionAccepted versionen_US
dc.identifier.spage0806en_US
dc.identifier.epage0810en_US
dc.subject.keywordsApproximate Computingen_US
dc.subject.keywordsComputer Arithmeticen_US
dc.citation.conferencelocationJeju, Korea (South)en_US
dc.description.acknowledgementThis work is supported by the Singapore Ministry of Education (MOE) Academic Research Fund Tier 2 under grant MOE2017-T2-1-002 and MOE Tier 1 under grant RG132/16.en_US
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