Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/144005
Title: Speed, energy and area optimized early output quasi-delay-insensitive array multipliers
Authors: Balasubramanian, Padmanabhan
Maskell, Douglas Leslie
Mastorakis, N. E.
Keywords: Engineering::Computer science and engineering::Hardware
Issue Date: 2020
Source: Balasubramanian, P., Maskell, D. L., & Mastorakis, N. E. (2020). Speed, energy and area optimized early output quasi-delay-insensitive array multipliers. PloS One, 15(2), e0228343-. doi:10.1371/journal.pone.0228343
Project: MOE2017-T2-1-002
MOE2018-T2-2-024
Journal: PloS One
Abstract: Multiplication is a widely used arithmetic operation that is frequently encountered in micro-processing and digital signal processing. Multiplication is implemented using a multiplier, and recently, QDI asynchronous array multipliers were presented in the literature utilizing delay-insensitive double-rail data encoding and four-phase return-to-zero (RTZ) handshaking and four-phase return-to-one (RTO) handshaking. In this context, this article makes two contributions: (i) the design of a new asynchronous partial product generator, and (ii) the design of a new asynchronous half adder. We analyze the usefulness of the proposed partial product generator and the proposed half adder to efficiently realize QDI array multipliers. When the new partial product generator and half adder are used along with our indicating full adder, significant reductions are achieved in the design metrics compared to the optimum QDI array multiplier reported in the literature. The cycle time is reduced by 17%, the area is reduced by 16.1%, the power is reduced by 15.3%, and the product of power and cycle time is reduced by 29.6% with respect to RTZ handshaking. On the other hand, the cycle time is reduced by 13%, the area is reduced by 16.1%, the power is reduced by 15.2%, and the product of power and cycle time is reduced by 26.1% with respect to RTO handshaking. Further, the RTO handshaking is found to be preferable to RTZ handshaking to achieve slightly improved optimizations in the design metrics. The QDI array multipliers were realized using a 32/28nm complementary metal oxide semiconductor (CMOS) process technology.
URI: https://hdl.handle.net/10356/144005
ISSN: 1932-6203
DOI: 10.1371/journal.pone.0228343
Rights: © 2020 Balasubramanian et al. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:SCSE Journal Articles

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