Please use this identifier to cite or link to this item:
Full metadata record
DC FieldValueLanguage
dc.contributor.authorBalasubramanian, Padmanabhanen_US
dc.contributor.authorMaskell, Douglas Leslieen_US
dc.contributor.authorMastorakis, N. E.en_US
dc.identifier.citationBalasubramanian, P., Maskell, D. L., & Mastorakis, N. E. (2020). Speed, energy and area optimized early output quasi-delay-insensitive array multipliers. PloS One, 15(2), e0228343-. doi:10.1371/journal.pone.0228343en_US
dc.description.abstractMultiplication is a widely used arithmetic operation that is frequently encountered in micro-processing and digital signal processing. Multiplication is implemented using a multiplier, and recently, QDI asynchronous array multipliers were presented in the literature utilizing delay-insensitive double-rail data encoding and four-phase return-to-zero (RTZ) handshaking and four-phase return-to-one (RTO) handshaking. In this context, this article makes two contributions: (i) the design of a new asynchronous partial product generator, and (ii) the design of a new asynchronous half adder. We analyze the usefulness of the proposed partial product generator and the proposed half adder to efficiently realize QDI array multipliers. When the new partial product generator and half adder are used along with our indicating full adder, significant reductions are achieved in the design metrics compared to the optimum QDI array multiplier reported in the literature. The cycle time is reduced by 17%, the area is reduced by 16.1%, the power is reduced by 15.3%, and the product of power and cycle time is reduced by 29.6% with respect to RTZ handshaking. On the other hand, the cycle time is reduced by 13%, the area is reduced by 16.1%, the power is reduced by 15.2%, and the product of power and cycle time is reduced by 26.1% with respect to RTO handshaking. Further, the RTO handshaking is found to be preferable to RTZ handshaking to achieve slightly improved optimizations in the design metrics. The QDI array multipliers were realized using a 32/28nm complementary metal oxide semiconductor (CMOS) process technology.en_US
dc.description.sponsorshipMinistry of Education (MOE)en_US
dc.relation.ispartofPloS Oneen_US
dc.rights© 2020 Balasubramanian et al. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.en_US
dc.subjectEngineering::Computer science and engineering::Hardwareen_US
dc.titleSpeed, energy and area optimized early output quasi-delay-insensitive array multipliersen_US
dc.typeJournal Articleen
dc.contributor.schoolSchool of Computer Science and Engineeringen_US
dc.description.versionPublished versionen_US
dc.subject.keywordsCircuit Designen_US
dc.description.acknowledgementThis work was supported by grants MOE2017-T2-1-002 and MOE2018-T2-2-024, Ministry of Education (MOE), Singapore.en_US
item.fulltextWith Fulltext-
Appears in Collections:SCSE Journal Articles
Files in This Item:
File Description SizeFormat 
journal.pone.0228343.pdfPublished version3.54 MBAdobe PDFThumbnail

Citations 50

Updated on Mar 16, 2023

Web of ScienceTM
Citations 50

Updated on Mar 16, 2023

Page view(s)

Updated on Mar 22, 2023

Download(s) 50

Updated on Mar 22, 2023

Google ScholarTM




Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.