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Title: A 3GS/s highly linear energy efficient constant-slope based voltage-to-time converter
Authors: Chen, Qian
Liang, Yuan
Kim, Bongjin
Boon, Chirn Chye
Keywords: Engineering::Electrical and electronic engineering::Integrated circuits
Issue Date: 2020
Source: Chen, Q., Liang, Y., Kim, B., & Boon, C. C. (2020). A 3GS/s highly linear energy efficient constant-slope based voltage-to-time converter. Proceedings of the 2020 The IEEE International Symposium on Circuits and Systems (ISCAS). doi:10.1109/ISCAS45731.2020.9180535
Project: MOE2019-T2- 1-114
Abstract: This paper presents a high speed highly linear energy-efficient constant-slope based voltage-to-time converter (VTC). By combining sample-and-hold with constant charging process, we achieve precise sampled step and linear charging ramp concurrently without using the extra control clock. Simple calibration has been implemented to overcome conversion gain variation due to process-voltage-temperature (PVT) variation. The post-layout simulation results show that the SFDR/-THD of the proposed VTC reaches 58.7dB/56.3dB at 3GS/s near Nyquist (typical corner). The VTC achieves 144ps output range with 0.83mW power consumption at 3GHz. It occupies an active area of 41.3um × 34.4um implemented in 65nm CMOS.
DOI: 10.1109/ISCAS45731.2020.9180535
Rights: © 2020 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work is available at:
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Conference Papers

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