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Title: A dc-reactor-based solid-state fault current limiter for HVdc applications
Authors: Heidary, Amir
Radmanesh, Hamid
Rouzbehi, Kumars
Pou, Josep
Keywords: Engineering::Electrical and electronic engineering
Issue Date: 2019
Source: Heidary, A., Radmanesh, H., Rouzbehi, K., & Pou, J. (2019). A dc-reactor-based solid-state fault current limiter for HVdc applications. IEEE Transactions on Power Delivery, 34(2), 720-728. doi:10.1109/tpwrd.2019.2894521
Journal: IEEE Transactions on Power Delivery
Abstract: Expansion of high-voltage dc (HVdc) systems to multi-terminal HVdc (MT-HVdc) systems/grids considerably increases the short-circuit levels. In order to protect the emerging MT-HVdc systems/grids against fault currents, proper dc fault current limiters (FCLs) must be developed. This paper proposes an innovative high inductance solid-state dc-reactor-based FCL (HISS-DCRFCL) to be used in HVdc applications. In fact, during the HISS-DCRFCL normal operation, its inductance value is extremely low, and its value becomes considerably high during the fault period, which decreases the fault current amplitude. The proposed HISS-DCRFCL performance is analyzed by MATLAB/Simulink and the simulation results are verified and confirmed by laboratory experimental results using a scaled-down laboratory prototype setup.
ISSN: 0885-8977
DOI: 10.1109/TPWRD.2019.2894521
Schools: School of Electrical and Electronic Engineering 
Rights: © 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at:
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Journal Articles

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