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Title: Energy-efficient crypto acceleration with HW/SW co-design for HTTPS
Authors: Xiao, Chunhua
Zhang, Lei
Liu, Weichen
Bergmann, Neil
Xie, Yuhua
Keywords: Engineering::Computer science and engineering
Issue Date: 2019
Source: Xiao, C., Zhang, L., Liu, W., Bergmann, N., & Xie, Y. (2019). Energy-efficient crypto acceleration with HW/SW co-design for HTTPS. Future Generation Computer Systems, 96, 336-347. doi:10.1016/j.future.2019.02.023
Journal: Future Generation Computer Systems
Abstract: Entering the Big Data era leads to the rapid development of web applications which provide high-performance sensitive access on large cloud data centers. HTTPS has been widely deployed as an extension of HTTP by adding an encryption layer of SSL/TLS protocol for secure communication over the Internet. To accelerate the complex crypto computation, specific acceleration instruction set and hardware accelerator are adopted. However, energy consumption has been ignored in the rush for performance. Actually, energy efficiency has become a challenge with the increasing demands for performance and energy saving in data centers. In this paper, we present the EECA, an Energy-Efficient Crypto Acceleration system for HTTPS with OpenSSL. It provides high energy-efficient encryption through HW/SW co-design. The essential idea is to make full use of system resource to exert the superiorities of different crypto acceleration approaches for an energy-efficient design. Experimental results show that, if only do crypto computations with typical encryption algorithm AES-256-CBC, the proposed EECA could get up to 1637.13%, 84.82%, and 966.23% PPW (Performance per Watt) improvement comparing with original software encryption, instruction set acceleration and hardware accelerator, respectively. If considering the whole working flow for end-to-end secure HTTPS based on OpenSSL with cipher suite ECDHE-RSA-AES256-SHA384, EECA could also improve the energy efficiency by up to 422.26%, 40.14% and 96.05% comparing with the original Web server using software, instruction set and hardware accelerators, respectively.
ISSN: 0167-739X
DOI: 10.1016/j.future.2019.02.023
Rights: © 2019 Elsevier B.V. All rights reserved.
Fulltext Permission: none
Fulltext Availability: No Fulltext
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