Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/145115
Title: Design and realization of low dropout voltage regulators in PMIC for portable applications
Authors: Li, Kan
Keywords: Engineering::Electrical and electronic engineering
Issue Date: 2020
Publisher: Nanyang Technological University
Source: Li, K. (2020). Design and realization of low dropout voltage regulators in PMIC for portable applications. Doctoral thesis, Nanyang Technological University, Singapore.
Abstract: Power Management Integrated Circuit (PMIC) is becoming increasingly important in modern moblie applications because high-quality power supply is increasingly demanded by mobile electronics such as System-on-Chips (SoCs), Mobile Station Modem (MSM), camera image sensor, etc. Low DropOut linear regulators (LDOs) is one of the most critical modules in PMIC that ascertain the quality of the power supply of the said mobile electronic. Note that PMIC first steps down the battery voltage to a lower regulated voltage by high efficiency but noisy switching regulators. Thereafter, LDO follows the switching regulators to filter out the switching component of the output of the swiching regulator to generate a low-noise, high quality supply voltage. Amongst all the design metrics of LDO, a fast load transient response with small overshoot/undershoot is arguabely the most important yet challenging specification for LDO to achieve. This is mainly due to two reasons. Firstly, modern mobile SoC is becoming more and more complex with higher computional capability. This leads to a large current consumption and fast switching activity, which demands LDO to handle large load step/attack (e.g., 1A/1μs). Secondly, moblie electronics are exploiting the advanced semiconductor fabraction process where the supply voltage is small and less tolerable to supply spike/noise. This Ph.D work pertains to the investigation and study of various design techniques for high performacne LDO achieving superior load transient response that is suitable for modern mobile application. Specifically, three fast transient LDO designs embodying three novel design techiniques are developed and vii proposed: 1. The first proposed LDO achieves fast transient response by using a high swing dynamic biasing impedance-attenuation buffer. The impedance-attenuation buffer helps the loop stability and improves the transient response. The buffer’s feature of rail-to-rail swing makes the LDO’s power FET size smaller than traditional buffer design for the same current deliverability. This thesis also analyzes its design robustness in terms of stability and offset. A low-cost trim method is also introduced to achieve a high yield for potential production. This LDO with high swing dynamic biasing impedance-attenuation buffer has been fabricated in 0.18-μm HV CMOS process. The silicon size of the LDO is 137000 μm2. The LDO’s quiescent current is 15μA and can deliver up to 600mA loading current. The maximum transient output voltage variation is 1.5% with a load step of 500mA/100ns. 2. The second proposed LDO is a dual-loop compensated, fast-transient LDO. It is successfully implemented in a 0.18-μm CMOS process with a total silicon area of 210 μm × 593 μm. The proposed LDO is composed of two feedback loops. The fast feedback loop (FFL) employs direct output voltage spike detection through the capacitive coupling, resulting in significantly improved, large-signal transient response and loop bandwidth at the same time. Its voltage spike is 15 mV for a load step of 600 mA. The proposed LDO has a loop bandwidth of 2.3 MHz at a load current of 600 mA with a 30 μA quiescent current. A power transistor with the pseudo-equivalent series resistance (ESR) technique is proposed
URI: https://hdl.handle.net/10356/145115
DOI: 10.32657/10356/145115
Rights: This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License (CC BY-NC 4.0).
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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