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|Title:||A 0.4-V, 0.138-fJ/cycle single-phase-clocking redundant-transition-free 24T flip-flop with change-sensing scheme in 40-nm CMOS||Authors:||Le, Van Loi
Kim, Tony Tae-Hyoung
|Keywords:||Engineering::Electrical and electronic engineering||Issue Date:||2018||Source:||Le, V. L., Li, J., Chang, A., & Kim, T. T.-H. (2018). A 0.4-V, 0.138-fJ/cycle single-phase-clocking redundant-transition-free 24T flip-flop with change-sensing scheme in 40-nm CMOS.||Journal:||IEEE Journal of Solid-State Circuits||Abstract:||This paper presents an extremely low-voltage and low-power single-phase-clocking redundant-transition-free flip-flop (FF), named change-sensing FF (CSFF). By utilizing a local change-sensing scheme for eliminating redundant transitions of internal clocked nodes, CSFF does not consume any dynamic power when there is no data activity. Measurement results from a test chip fabricated in 40-nm CMOS technology show that CSFF saves up to 90% power dissipation at 5% data activity without additional transistors compared to the conventional transmission-gate FF (TGFF). CSFF consumes only 0.138 fJ/cycle, which is 84% lower than that of TGFF, at 0.4 V and 10% activity. In addition to the significant improvement in power and energy efficiencies, CSFF also enhances performance and minimum operating voltage. The test chip measurement demonstrates successful operations of CSFF down to 0.19 V and the delay improvement of 37% compared to TGFF in the supply voltage range of 0.4-1 V.||URI:||https://hdl.handle.net/10356/145239||ISSN:||1558-173X||DOI:||10.1109/JSSC.2018.2863946||Rights:||© 2018 Institute of Electrical and Electronics Engineers (IEEE). All rights reserved.||Fulltext Permission:||none||Fulltext Availability:||No Fulltext|
|Appears in Collections:||EEE Journal Articles|
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