Please use this identifier to cite or link to this item:
|Title:||An energy-efficient current-starved inverter based strong physical unclonable function with enhanced temperature stability||Authors:||Cao, Yuan
|Keywords:||Engineering::Electrical and electronic engineering||Issue Date:||2019||Source:||Cao, Y., Zheng, W., Zhao, X., & Chang, C.-H. (2019). An energy-efficient current-starved inverter based strong physical unclonable function with enhanced temperature stability. IEEE Access, 7, 105287-105297. doi:10.1109/ACCESS.2019.2932022||Project:||MOE2015-T2-013||Journal:||IEEE Access||Abstract:||As burgeoning hardware security primitive, physical unclonable function (PUF) has aroused the interest of solid-state circuit community on its efficient integration into security-critical applications. This paper presents an energy efficient implementation of classic arbiter PUF design. Current-starved (CS) inverters are inserted at the inputs of each multiplexer cell to reduce the skew and widen the distribution of the delay difference between two symmetric daisy-chained delay paths selectable by the input challenge. The CS-inverters are biased at the zero temperature coefficient (ZTC) point, making the accumulated delays of the two identical paths insensitive to temperature variations. A symmetric two RS latches based arbiter is proposed to overcome the asymmetric input and clock to the output propagation delay of D flip-flop and the metastability problem of RS latch arbiter. By limiting the drain currents of CS-inverters to achieve ZTC, the power consumption of the proposed PUF is also reduced substantially. The performance of the proposed PUF design has been successfully validated by the responses measured from prototype chips fabricated in standard 65 nm CMOS process. The fabricated chips feature a compact silicon area of 3838 μm 2 and low energy consumption of 2.74 pJ per bit at 25 Mbps, with measured uniqueness of 46.8% and native bit error rate (BER) of 0.8%. It is worst-case BER is less than 10.46% measured over an extended ~7× temperature range and ~5× supply voltage range. These physically measured figures of merit have outperformed previously reported measurements of strong PUFs with similar linear additive delay architecture.||URI:||https://hdl.handle.net/10356/145618||ISSN:||2169-3536||DOI:||10.1109/ACCESS.2019.2932022||Rights:||© 2019 IEEE. This journal is 100% open access, which means that all content is freely available without charge to users or their institutions. All articles accepted after 12 June 2019 are published under a CC BY 4.0 license, and the author retains copyright. Users are allowed to read, download, copy, distribute, print, search, or link to the full texts of the articles, or use them for any other lawful purpose, as long as proper attribution is given.||Fulltext Permission:||open||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Journal Articles|
Updated on Apr 20, 2021
Updated on Apr 20, 2021
Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.