Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/145827
Title: A 1036-F2/bit high reliability temperature compensated cross-coupled comparator-based PUF
Authors: Zhao, Qiang
Wu, Yiheng
Zhao, Xiaojin
Cao, Yuan
Chang, Chip-Hong
Keywords: Engineering::Electrical and electronic engineering
Issue Date: 2020
Source: Zhao, Q., Wu, Y., Zhao, X., Cao, Y., & Chang, C.-H. (2020). A 1036-F2/bit high reliability temperature compensated cross-coupled comparator-based PUF. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 28(6), 1449-1460. doi:10.1109/TVLSI.2020.2980306
Project: MOE2018-T1-001-131, RG87/18-(S)
Journal: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Abstract: In this article, a compact physical unclonable function (PUF) based on cross-coupled comparator is presented. Featuring a positive feedback response generation mechanism, the mismatch in analog signals between the cross-coupled transistor pair is quickly amplified to prevent its polarity from flipping by the temporal noise. The rapid enlargement of noise margin by the sense amplifier also contributes to stabilizing the response against supply voltage variations. To improve its temperature stability, the counteracting effect of complementary-to-absolute temperature (CTAT) and proportional-to-absolute-temperature (PTAT) drives are considered in sizing the bit cell transistors. The proposed design is fabricated in a standard 65-nm CMOS process. The bit cell occupies an area of only 4.38 µm2 (i.e., 1036 F2), and the overall PUF chip consumes 2.98 pJ/bit at the throughput of 8 Mb/s, of which only 1.61 pJ/bit is due to the PUF’s core. With the uniqueness measured to be 49.53%, the unpredictability of the fabricated PUF chips is validated by autocorrelation function and NIST randomness tests. Compared with the state-of-the-art implementations, the proposed PUF has the lowest native response instability of 1.46% with 500 repeated PUF readouts at 27 ◦C and 1.2 V. By varying the operating temperature from −50 ◦C to 150 ◦C in a step size of 10 ◦C and the supply voltage from 1.0 to 1.4 V in a step size of 0.1 V simultaneously, the average reliability of the proposed PUF obtained from the 2-D plot of all operating conditions is found to be 96.87% without correction and 99.31% with spatial majority voting (SMV).
URI: https://hdl.handle.net/10356/145827
ISSN: 1557-9999
DOI: 10.1109/TVLSI.2020.2980306
Rights: © 2020 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: https://doi.org/10.1109/TVLSI.2020.2980306
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Journal Articles

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