Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/146876
Title: High-throughput and area-optimized architecture for rBRIEF feature extraction
Authors: Pham, Thinh Hung
Tran, Phong
Lam, Siew-Kei
Keywords: Engineering::Computer science and engineering
Issue Date: 2019
Source: Pham, T. H., Tran, P. & Lam, S. (2019). High-throughput and area-optimized architecture for rBRIEF feature extraction. IEEE Transactions On Very Large Scale Integration (VLSI) Systems, 27(4), 747-756. https://dx.doi.org/10.1109/TVLSI.2018.2881105
Journal: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Abstract: Feature matching is a fundamental step in many real-time computer vision applications such as simultaneous localization and mapping, motion analysis, and stereo correspondence. The performance of these applications depends on the distinctiveness of the visual feature descriptors used, and the speed at which they can be extracted from video frames. When combined with standard key-point detectors, the rotation-aware binary robust independent elementary features (rBRIEF) descriptor has been shown to outperform its counterparts. In this paper, we present a deep-pipelined stream processing architecture that is capable of extracting rBRIEF features from high-throughput video frames. To achieve high processing rate and low complexity hardware, the proposed architecture incorporates an enhanced moving summation strategy to calculate the key-points' patch moments and employs approximate computations to achieve patch rotation. Multiplier-less circuitry is introduced throughout the architecture to avoid the use of costly multipliers. Implementation on the Altera Aria V device demonstrates that the proposed architecture leads to 53.3% reduction in hardware resources (adaptive logic modules), while achieving 50% higher accuracy (in terms of average Hamming distance) when compared to the state-of-the-art architecture. In addition, the proposed architecture is able to process high-resolution (1920 × 1080) images at 60 fps, while consuming only 456.15 mW power.
URI: https://hdl.handle.net/10356/146876
ISSN: 1063-8210
DOI: 10.1109/TVLSI.2018.2881105
Rights: © 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: https://doi.org/10.1109/TVLSI.2018.2881105.
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:SCSE Journal Articles

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