Please use this identifier to cite or link to this item:
https://hdl.handle.net/10356/146876
Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Pham, Thinh Hung | en_US |
dc.contributor.author | Tran, Phong | en_US |
dc.contributor.author | Lam, Siew-Kei | en_US |
dc.date.accessioned | 2021-03-12T05:39:59Z | - |
dc.date.available | 2021-03-12T05:39:59Z | - |
dc.date.issued | 2019 | - |
dc.identifier.citation | Pham, T. H., Tran, P. & Lam, S. (2019). High-throughput and area-optimized architecture for rBRIEF feature extraction. IEEE Transactions On Very Large Scale Integration (VLSI) Systems, 27(4), 747-756. https://dx.doi.org/10.1109/TVLSI.2018.2881105 | en_US |
dc.identifier.issn | 1063-8210 | en_US |
dc.identifier.other | 0000-0003-1836-3363 | - |
dc.identifier.other | 0000-0001-7632-5600 | - |
dc.identifier.other | 0000-0002-8346-2635 | - |
dc.identifier.uri | https://hdl.handle.net/10356/146876 | - |
dc.description.abstract | Feature matching is a fundamental step in many real-time computer vision applications such as simultaneous localization and mapping, motion analysis, and stereo correspondence. The performance of these applications depends on the distinctiveness of the visual feature descriptors used, and the speed at which they can be extracted from video frames. When combined with standard key-point detectors, the rotation-aware binary robust independent elementary features (rBRIEF) descriptor has been shown to outperform its counterparts. In this paper, we present a deep-pipelined stream processing architecture that is capable of extracting rBRIEF features from high-throughput video frames. To achieve high processing rate and low complexity hardware, the proposed architecture incorporates an enhanced moving summation strategy to calculate the key-points' patch moments and employs approximate computations to achieve patch rotation. Multiplier-less circuitry is introduced throughout the architecture to avoid the use of costly multipliers. Implementation on the Altera Aria V device demonstrates that the proposed architecture leads to 53.3% reduction in hardware resources (adaptive logic modules), while achieving 50% higher accuracy (in terms of average Hamming distance) when compared to the state-of-the-art architecture. In addition, the proposed architecture is able to process high-resolution (1920 × 1080) images at 60 fps, while consuming only 456.15 mW power. | en_US |
dc.description.sponsorship | National Research Foundation (NRF) | en_US |
dc.language.iso | en | en_US |
dc.relation.ispartof | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | en_US |
dc.rights | © 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: https://doi.org/10.1109/TVLSI.2018.2881105. | en_US |
dc.subject | Engineering::Computer science and engineering | en_US |
dc.title | High-throughput and area-optimized architecture for rBRIEF feature extraction | en_US |
dc.type | Journal Article | en |
dc.contributor.school | School of Computer Science and Engineering | en_US |
dc.identifier.doi | 10.1109/TVLSI.2018.2881105 | - |
dc.description.version | Accepted version | en_US |
dc.identifier.scopus | 2-s2.0-85058104769 | - |
dc.identifier.issue | 4 | en_US |
dc.identifier.volume | 27 | en_US |
dc.identifier.spage | 747 | en_US |
dc.identifier.epage | 756 | en_US |
dc.subject.keywords | Feature Extraction | en_US |
dc.subject.keywords | Computer Architecture | en_US |
dc.description.acknowledgement | This research project is partially funded by the NationalResearch Foundation Singapore under its Campus for Re-search Excellence and Technological Enterprise (CREATE)programme. | en_US |
item.fulltext | With Fulltext | - |
item.grantfulltext | open | - |
Appears in Collections: | SCSE Journal Articles |
Files in This Item:
File | Description | Size | Format | |
---|---|---|---|---|
High throughput and area optimized architecture for rbrief feature extraction.pdf | 1.71 MB | Adobe PDF | View/Open |
SCOPUSTM
Citations
20
18
Updated on Mar 25, 2024
Web of ScienceTM
Citations
20
14
Updated on Oct 29, 2023
Page view(s)
212
Updated on Mar 28, 2024
Download(s) 50
112
Updated on Mar 28, 2024
Google ScholarTM
Check
Altmetric
Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.