Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/146876
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dc.contributor.authorPham, Thinh Hungen_US
dc.contributor.authorTran, Phongen_US
dc.contributor.authorLam, Siew-Keien_US
dc.date.accessioned2021-03-12T05:39:59Z-
dc.date.available2021-03-12T05:39:59Z-
dc.date.issued2019-
dc.identifier.citationPham, T. H., Tran, P. & Lam, S. (2019). High-throughput and area-optimized architecture for rBRIEF feature extraction. IEEE Transactions On Very Large Scale Integration (VLSI) Systems, 27(4), 747-756. https://dx.doi.org/10.1109/TVLSI.2018.2881105en_US
dc.identifier.issn1063-8210en_US
dc.identifier.other0000-0003-1836-3363-
dc.identifier.other0000-0001-7632-5600-
dc.identifier.other0000-0002-8346-2635-
dc.identifier.urihttps://hdl.handle.net/10356/146876-
dc.description.abstractFeature matching is a fundamental step in many real-time computer vision applications such as simultaneous localization and mapping, motion analysis, and stereo correspondence. The performance of these applications depends on the distinctiveness of the visual feature descriptors used, and the speed at which they can be extracted from video frames. When combined with standard key-point detectors, the rotation-aware binary robust independent elementary features (rBRIEF) descriptor has been shown to outperform its counterparts. In this paper, we present a deep-pipelined stream processing architecture that is capable of extracting rBRIEF features from high-throughput video frames. To achieve high processing rate and low complexity hardware, the proposed architecture incorporates an enhanced moving summation strategy to calculate the key-points' patch moments and employs approximate computations to achieve patch rotation. Multiplier-less circuitry is introduced throughout the architecture to avoid the use of costly multipliers. Implementation on the Altera Aria V device demonstrates that the proposed architecture leads to 53.3% reduction in hardware resources (adaptive logic modules), while achieving 50% higher accuracy (in terms of average Hamming distance) when compared to the state-of-the-art architecture. In addition, the proposed architecture is able to process high-resolution (1920 × 1080) images at 60 fps, while consuming only 456.15 mW power.en_US
dc.description.sponsorshipNational Research Foundation (NRF)en_US
dc.language.isoenen_US
dc.relation.ispartofIEEE Transactions on Very Large Scale Integration (VLSI) Systemsen_US
dc.rights© 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: https://doi.org/10.1109/TVLSI.2018.2881105.en_US
dc.subjectEngineering::Computer science and engineeringen_US
dc.titleHigh-throughput and area-optimized architecture for rBRIEF feature extractionen_US
dc.typeJournal Articleen
dc.contributor.schoolSchool of Computer Science and Engineeringen_US
dc.identifier.doi10.1109/TVLSI.2018.2881105-
dc.description.versionAccepted versionen_US
dc.identifier.scopus2-s2.0-85058104769-
dc.identifier.issue4en_US
dc.identifier.volume27en_US
dc.identifier.spage747en_US
dc.identifier.epage756en_US
dc.subject.keywordsFeature Extractionen_US
dc.subject.keywordsComputer Architectureen_US
dc.description.acknowledgementThis research project is partially funded by the NationalResearch Foundation Singapore under its Campus for Re-search Excellence and Technological Enterprise (CREATE)programme.en_US
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