Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/146916
Full metadata record
DC FieldValueLanguage
dc.contributor.authorBalasubramanian, Padmanabhanen_US
dc.contributor.authorNayar, Raunaqen_US
dc.contributor.authorMaskell, Douglas Leslieen_US
dc.date.accessioned2021-03-15T02:25:54Z-
dc.date.available2021-03-15T02:25:54Z-
dc.date.issued2021-
dc.identifier.citationBalasubramanian, P., Nayar, R. & Maskell, D. L. (2021). Approximate array multipliers. Electronics, 10(5), 630:1-630:20. https://dx.doi.org/10.3390/electronics10050630en_US
dc.identifier.issn2079-9292en_US
dc.identifier.urihttps://hdl.handle.net/10356/146916-
dc.description.abstractThis article describes the design of approximate array multipliers by making vertical or horizontal cuts in an accurate array multiplier followed by different input and output assignments within the multiplier. We consider a digital image denoising application and show how different combinations of input and output assignments in an approximate array multiplier affect the quality of the denoised images. We consider the accurate array multiplier and several approximate array multipliers for synthesis. The multipliers were described in Verilog hardware description language and synthesized by Synopsys Design Compiler using a 32/28-nm complementary metal-oxide-semiconductor technology. The results show that compared to the accurate array multiplier, one of the proposed approximate array multipliers viz. PAAM01-V7 achieves a 28% reduction in critical path delay, 75.8% reduction in power, and 64.6% reduction in area while enabling the production of a denoised image that is comparable in quality to the image denoised using the accurate array multiplier. The standard design metrics such as critical path delay, total power dissipation, and area of the accurate and approximate multipliers are given, the error parameters of the approximate array multipliers are provided, and the original image, the noisy image, and the denoised images are also depicted for comparison.en_US
dc.description.sponsorshipMinistry of Education (MOE)en_US
dc.language.isoenen_US
dc.relationMOE2018-T2-2-024en_US
dc.relation.ispartofElectronicsen_US
dc.rights© 2021 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https://creativecommons.org/licenses/by/4.0/).en_US
dc.subjectEngineering::Electrical and electronic engineering::Integrated circuitsen_US
dc.subjectEngineering::Computer science and engineering::Hardwareen_US
dc.titleApproximate array multipliersen_US
dc.typeJournal Articleen
dc.contributor.schoolSchool of Computer Science and Engineeringen_US
dc.contributor.researchHardware & Embedded Systems Lab (HESL)en_US
dc.identifier.doi10.3390/electronics10050630-
dc.description.versionPublished versionen_US
dc.identifier.issue5en_US
dc.identifier.volume10en_US
dc.identifier.spage630:1en_US
dc.identifier.epage630:20en_US
dc.subject.keywordsArithmetic Circuitsen_US
dc.subject.keywordsApproximate Computingen_US
dc.description.acknowledgementThis research was funded by the Ministry of Education, Singapore under grant number MOE2018-T2-2-024.en_US
item.fulltextWith Fulltext-
item.grantfulltextopen-
Appears in Collections:SCSE Journal Articles
Files in This Item:
File Description SizeFormat 
electronics-10-00630-v2.pdfPublished version7.24 MBAdobe PDFView/Open

SCOPUSTM   
Citations 20

8
Updated on Dec 2, 2022

Web of ScienceTM
Citations 50

4
Updated on Dec 6, 2022

Page view(s)

195
Updated on Dec 8, 2022

Download(s) 50

29
Updated on Dec 8, 2022

Google ScholarTM

Check

Altmetric


Plumx

Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.