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|Title:||Design of a handshake asynchronous IC design tool||Authors:||Ho, Weng Geng.||Keywords:||DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits||Issue Date:||2008||Abstract:||The report has elaborated the Final Year Project (FYP), namely Design of a Handshake Asynchronous IC design tool. The use of a Handshake Solutions TiDE AE Asynchronous IC Design CAD tools and the methodology for designing VLSI systems were explored. Input language for Handshake Solutions, Haste and its syntax in various applications were learned. The overview of the Handshake Solutions TiDE AE tools and their design flow was conducted and summarized. The process of design includes compilation, mapping, simulation, analysis, modules linking, logic optimization and timing validation. For a simple illustration of design flow, simple Buffer Gate circuit was designed and verified. Besides, design of complex asynchronous VLSI circuit, FIR filter was later conducted for further exploration. The architecture of the design, design steps as well as the results of various processes has been discussed. Comments and conclusions of the whole project were also included in the report.||URI:||http://hdl.handle.net/10356/14725||Fulltext Permission:||restricted||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Student Reports (FYP/IA/PA/PI)|
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