Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/147421
Title: Neural network-based inherently fault-tolerant hardware cryptographic primitives without explicit redundancy checks
Authors: Alam, Manaar
Bag, Arnab
Roy, Debapriya Basu
Jap, Dirmanto
Breier, Jakub
Bhasin, Shivam
Mukhopadhyay, Debdeep
Keywords: Engineering::Computer science and engineering
Issue Date: 2020
Source: Alam, M., Bag, A., Roy, D. B., Jap, D., Breier, J., Bhasin, S. & Mukhopadhyay, D. (2020). Neural network-based inherently fault-tolerant hardware cryptographic primitives without explicit redundancy checks. ACM Journal On Emerging Technologies in Computing Systems, 17(1), 1-30. https://dx.doi.org/10.1145/3409594
Journal: ACM Journal on Emerging Technologies in Computing Systems
Abstract: Fault injection-based cryptanalysis is one of the most powerful practical threats to modern cryptographic primitives. Popular countermeasures to such fault-based attacks generally use some formof redundant computation to detect and react/correct the injected faults. However, such countermeasures are shown to be vulnerable to selective fault injections. In this article, we aim to develop acryptographic primitive that is fault tolerant by its construction and does not require to compute the same value multiple times. We utilize the effectiveness of Neural Networks (NNs), which show "some degree"of robustness by functioning correctly even after the occurrence of faults inany of its parameters. We also propose a novel strategy that enhances the fault tolerance of the implementation to "high degree"(close to 100%) by incorporating selective constraints in the NN parameters during the training phase. We evaluated the performance of revised NN considering both software and FPGA implementations for standard cryptographic primitives like 8×8 AES SBox and 4×4 PRESENT SBox. The results show that the fault tolerance of such implementations canbe significantly increased with the proposed methodology. Such NN-based cryptographic primitives will provide inherent resistance against fault injections without requiring any redundancy countermeasures.
URI: https://hdl.handle.net/10356/147421
ISSN: 1550-4840
DOI: 10.1145/3409594
Rights: © 2020 Association for Computing Machinery (ACM). All rights reserved.
Fulltext Permission: none
Fulltext Availability: No Fulltext
Appears in Collections:TL Journal Articles

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